Quectel SG865W Series Hardware Design page 28

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WCD_SWR_TX_CLK 92
WCD_SWR_TX_DAT
91
A0
WCD_SWR_TX_DAT
87
A1
WCD_SWR_RX_CLK 82
WCD_SWR_RX_DAT
85
A0
WCD_SWR_RX_DAT
81
A1
LPI_DMIC3_CLK
46
LPI_DMIC3_DATA
52
I2S Interfaces
Pin Name
Pin No.
LPI_MI2S1_SCLK
62
LPI_MI2S1_WS
58
LPI_MI2S1_DATA0
67
LPI_MI2S1_DATA1
61
MI2S0_MCLK
63
MI2S0_SCLK
64
MI2S0_WS
80
MI2S0_DATA0
70
MI2S0_DATA1
75
MI2S2_SCLK
73
MI2S2_WS
68
MI2S2_DATA0
69
MI2S2_DATA1
74
SG865W_Series_Hardware_Design
WCD SoundWire
DO
transmit clock
WCD SoundWire
DIO
transmit data 0
WCD SoundWire
DIO
transmit data 1
WCD SoundWire
DO
receive clock
WCD SoundWire
DIO
receive data 0
WCD SoundWire
DIO
receive data 1
LPI digital MIC3
DO
clock
DI
LPI digital MIC3 data
I/O
Description
DO
LPI MI2S1 bit clock
LPI MI2S1 word
DO
select
LPI MI2S1 data
DIO
channel 0
LPI MI2S1 data
DIO
channel 1
DO
MI2S0 master clock
DO
MI2S0 bit clock
DO
MI2S0 word select
MI2S0 data channel
DIO
0
MI2S0 data channel
DIO
1
DO
MI2S2 bit clock
DO
MI2S2 word select
MI2S2 data channel
DIO
0
MI2S2 data channel
DIO
1
DC Characteristics
Comment
Smart Module Series
27 / 117

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