Central Processor Module Features - HP 3000 III Series Manual

System/CPU Overview
Table 2-1. Central Processor Module Features
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ARCHITECTURE
Hardware-implemented stack
Separate code and data
Non-mod ifiable reentr ant code
Variable-length code segmentation
Virtual memory for code
Dynamic relocatability of programs
IMPLEMENTATION
Microprogrammed CPU
175 nanosecond microinstruction time
Automatic restart after power failure
CTL Bus
Bus parity checking
Concurrent CPU and I/O operations
INSTRUCTIONS
209 ins tr uct ions
All instructions except stack operations are 16 bits
in length. (Stack operations can be packed two per
per word.)
16- and 32-bit integer arithmetic
32- and 64-bit floating point arithmetic
28-digit packed decimal arithmetic
Special instructions that optimize operating system
efficiency
:>r 2Al through 2A4 (HP 32435A Ser ies IIIL) are reserved for the
Lower Memory MOdule (Banks 0 - 7) and card cage slots 3A2 through
3A5 (HP 32421A Ser ies IlL) or 2A 7 through 2AIO (HP 324351\ Ser ies
III) are reserved for the Upper Memory Module (Banks 8 - 15).
2-12. MULTIPLEXER CHANNEL. The MUltiplexer Channels are design-
ed to operate with moderate-speed I/O devices. Each Multiplexer
Channel can handle up to 16 Device Controllers. The Multiplexer
Channel, in conjunction with the lOP, allows its associated De-
vice Controllers to run concurrently, interleaving their trans-
fers to or from Main Memory on a
wor~-by-word
basis. The
Multiplexer Channel resolves priority conflicts between its
associated Device Controllers for access to the lOP, translates
I/O program doubleword instructions into operating commands for
its Device Controllers, and maintains the operating status of
each Device Controller. Physically, the Multiplexer Channel con-
sists of one PCA which is conventionally installed in Card cage
No. 4 or 5 (depending on the computer system model) as shown in
tables 1-1 through 1-3. A detailed discussion of the Multiplexer
Channels is contained in Section VII.
2-5