HP 3000 III Series Manual page 296

I/O System
The Selector Channel control logic can now examine the order. If
the order specified in the 10CW is Read or Write and, if data
chaining is also specified, a pre-fetch sequence
IS
enabled.
This operation is the same as the fetch sequence described in the
preceding two paragraphs except that the returned data is loaded
into the 10CW Buffer and 10AW Buffer instead of the 10CW and 10AW
Active Registers. An additional condition for the pre-fetch se-
quence is that data transfer take precedence
~
i. e., pre-fetch
will occur only when both Input Buffers A and B are empty (for
Read) or both Output Buffers A and B are full (for Write). Then,
when the Read or Write order finishes, due either to word count
rollover or to a device end condition (see Read and Write execute
sequences), the 10CW/IOAW Buffers are read into the IOCW/IOAW
Active Registers. The data transfer can thus continue uninter-
rupted. If the new IOCW specifies further data chaining, another
pre-fetch is initiated to refill the buffers.
7-51. EXECUTE SEQUENCES. The following paragraphs contain
separate descriptions of the execute sequence for each of the
nine I/O orders. In each case except End, which terminates the
I/O program, operation returns to the fetch sequence following
completion in order to fetch the next I/O program word.
7-52. Sense. The Selector Olannel issues a P STATUS STB signal
to the Device Controller, with CHANSO, via the Selector Channel
Bus. The Device Controller accordingly reads the contents of its
Status Register onto the channel DATA lines and returns CHAN ACK
(Channel Acknowledge). On receipt of CHAN ACK, the Selector
Channel loads the status information into one of the two input
buffers and prepares for a memory transfer. First the contents
of the I/O Program Counter are decremented by one. This is
necessary because the status word must be stored in the IOAW
location for the current order, whereas the fetch sequence has
incremented the I/O Program Counter to point at the next word.
Once t~is is done, the contents of the I/O Program Counter and
the input buffer containing the status word are read out to the
channel PCD gates (but not gated out yet). The bank number be-
comes the TO address. A number is either loaded into the Bank
Register or Bank 0 is picked up at the Bank Gate (figure 7-19),
ga ted through the MOD select sw iches, and sent as the TO address
to the Port Controller via the TO lines of the Port Controller
Bus. A write request to the Port Controller requests a transmis-
sion to memory and, when the Port Controller returns ,LSEL, the
address from the I/O Program Counter is sent to memory and the
Counter is incremented. An HSEL from the Port Controller (which
follows immediately unless ENB has been preempted by a. higher-
priority module) then reads out the status word to the PCD lines
and sends it to memory. This stores Status in the IOAW location.
7-53. Interrupt. The Selector Channel control logic issues a P
SET INT signal to the Device Controller, with CHANSO, via the
Selector Channel Bus. The Device Controller returns CHAN ACK and
sets its Interrupt Request flip-flop. Provided the Mask flip-
flop is set, the Device Controller issues INT REQ to the lOP via
the lOP Bus. When the lOP returns INT POLL, the device number is
7-42