HP 3000 III Series Manual page 284

I/O System
to be decoded. The IOCMD in this case is SIO which, when decod-
ed, sets the Service Request (SR) flip-flop. The Service Request
(SR) along with a Request (REQ) signal is sent Multiplexer Chan-
nel Bus to the MUltiplexer Channel. (See figure 7-16.) The SR and
REQ cause the Multiplexer Channel, instead of the Device Control-
ler, to return SI and force a DRT FEtch to be the first operation
performed for the Device Controller on the next Service Request
from the Device Controller. An SIO to a Device Controller temp-
orarily inhibits service requests from all other Device Control-
lers. Therefore, the only Device Dontroller requesting is the
one receiving the SIO command. The Priority Encoder/Select De-
coder then issues a 4-bit binary code which corresponds to the SR
line number. The binary code is used as a RAM address to enable
one of the 16 locations in the solid-state mUltiplexer memory.
The solid-state memory contains separate RAM for each of the IOCW
and IOAW parts of the I/O program doubleword, and one to specify
the state (or next operation). In this case, a DRT fetch and an
Auxiliary RAM containing the I/O order. The IOCW is contained in
the Order RAM (16 bits), the IOAW is contained in the Address RAM
(16 bits) and the state is contained in the State RAM (4 bits).
Each of the addressable locations therefore contains 36-bits.
For the initialize operation, the State RAM location for the re-
questing device is forced to the condition required for a DRT
fetch. Once this is done, the Multiplexer Channel returns a DI
signal to the lOP, which in turn, causes the lOP to free the CPU
to execute other instructions. The Auxiliary RAM uses bits 12
through 15 of the Se t Bank I/O order on the IOD lines to send lOX
(B12 and B13) to the CPU Mod Select switches (see figure 7-10)
and to send lOX (B14 and B15) to memory (see figure 6-2) as part
of the IS-bit memory address. The lOP Mod Select Switches (fig-
ure 7-10) supply an IOTa signal to the MCU where it is gated to
memory (figure 6-2). The MUltiplexer Channel will transmit a
bank humber of 0 unles s actually moving data for a Read or Wr ite
order pair. In the following description, unless otherwise spec-
ified, the bank number will be considered to be zero.
7-35. DRT FETCH. The Service Request received at the Multiplexer
Channel from the Device Controller (figure 7-16) causes the
Transfer/Control Logic to send a Multiplexer Channel Service Re-
quest (HSREQ) to the lOP and also sets the SR latch. Any of the
16 SR inputs can set this latch and generate an HSREQ signal.
However, only the highest priority requests will be.honored by
the Priority Encoder. The lOP, when it receives an HSREQ, issues
a DATA POLL to all Multiplexer Channels. The highest priority
Multiplexer Channel stops the propagation of the poll (since SR
Latch is set), and its transfer logic is enabled. First, the
contents of the address RAM location are loaded into the State,
Address, Auxiliary, and Order Registers. The state bits tell the
transfer logic to send out a command to the Device Controller via
the MUltiplexer Channel Bus along with the Service Request number
signal (which is returned on the same line used for Service Re-
quest) and SO. This command tells the Device Controller to read
out its device number to the lOP Bus.
7-30