HP 3000 III Series Manual page 288

I/O System
MUltiplexer Channel to ask for data. Depending on the current
order, the
M~l
tiplexer Channel either ga tes the Order Register
contents out to the 100 lines (Return Residue order) or issues a
command to the Device Controller, telling it to read out its
Status Register contents (Sense or End orders). When either ac-
tion occurs, SI is returned to the lOP which causes the lOP to
load the 100 information into its Memory Data Input Register.
The lOP then proceeds to transmit this information to memory by
issuing IOHRQ to its MCU. When the transmission occurs, the ap-
propriate information will be stored into the IOAW location of
the I/O program doubleword.
7-40. Next Operation. At this point (after the IOAW fetch or
store), the I/O program word transfer is complete. In addition,
all orders except Read and Write (i.e., Control, Set Bank, Sense,
Return Residue, End, Jump, and Interrupt) are fully executed.
The next operation for any of these orders (except End, which
terminates the program) is to return to the DRT fetch operation.
For Read or Write, however, a data transfer is indicated.
7-41. DATA TRANSFERS. Data transfers are very similar to the I/O
program word transfers previously described, in that the basic
operation is to fetch or store information using a memory address
that has been put in the Address RAM by a. previous operation.
For I/O program word transfers, the previous operation was the
DRT fetch; for data transfers, the previous operation is the I/O
program word transfer. 'fhe main difference is that the data
transfer is device-initiated. That is, when a device is ready
for a transfer, it informs its Device Controller which then is-
sues an SR to the Multiplexer Channel. Another difference is
that the word count and memory address contained in the Order and
Address Registers must be· incremented during each word transfer.
Each data transfer consists of two distinct steps; the transfer
of an address to memory and the transfer of data to or from that
address. The first step (address to memory) is the same for ei-
ther output or input.
7-42. Address Transfer. When the device sets the Device Control-
ler's SR flip-flop, the SR signal to the Multiplexer Channel gen-
erates an HSREQ signal to the lOP. The lOP returns DATA POLL
which enables the MUltiplexer Channel to begin its transfer.
First, the addressed RAM location is read out to the State, Ad-
dress, Auxiliary, and Order Registers. Then the Address Register
contents are read out to the 100 lines and the Auxiliary Register
to the lOX lines. Also, SI and an appropriate IOCMD ("transfer
to memory" or "transfer from memory") are sent to the lOP. The
lOP loads the address and issues IOLRQ to its MCU with a Read/
Restore or a Clear/Write MOP. When priority allows, the MCU will
transmit the address to memory. Simultaneously, the Multiplexer
Channel resets the Device Controller's SR flip-flop via the Mul-
tiplexer Channel Bus and increments the Address and Order
Registers.
7-34