Ics-Type Internal Interrupt - HP 3000 III Series Manual

Interrupt System
(2) Passes an interrupt signal to the CPU.
(3) Turns on the external interrupt flag (Bit 8 in the CPXl
Register) •
(4) Drops the INT POLL signal.
If the device number equals zero, the lOP disregards the in-
terrupt signal and drops the INT POLL signal.
f. The lOP requests the CPU to set up the interrupt environment
(5). The initial steps are to set up the data segment
registers to point at the Interrupt Control Stack (after sav-
ing the user's environment on his own stack) and to fetch the
device's DRT entry.
g. The external program label in the second word of the DRT en-
try (6) is used to get the CST entry for the interrupt re-
ceiver code which, in turn, is used to set the PB-Bank, PB,
and PL Registers. The starting address for the interrupt
receiver code is obtained from the STT entry pointed to by
the external program label and is loaded into the P Register,
thus transferring control to the interrupt receiver code.
h. The information in the data area for this device (pointed to
by the third word of the DRT) (7) is upda ted by the inter rupt
receiver. This information will tell the I/O monitor process
that the initiator section of the device driver has done its
word and that the completion section should be called.
i. The interrupt receiver code IXITS (8) normally returns con-
trol back to the interrupted process (which may be another
interrupt or the Dispatcher). The interrupt receiver may al-
so request a new dispatch by executing a DISP instruction.
When an IXIT is executed by external interrupt code, a reset
command is sent to the appropriate device.
8-6. ICS Internal Interrupts
ICS-type internal interrupts operate on the ICS and the interrupt
code for each separate interrupt is permanently alloca ted in code
segment 1. (Refer to table 8-1.) Referring to the second example
in figure 8-2, the overall operation is as follows:
a. A condition such as power failure, stack overflow, or module
interrupt causes the CPU to switch to the ICS (1) after sav-
ing the user's environment on his own stack by creating an
Exte rnal Progr am Label which points to a Segment Tr ansfer
Table entry in the internal interrupt segment (CST entry 1) •
b. The PB and PL Registers are set up based on CST entry 1.
c. The Status Register is set to Pr ivileged Mode, Segment 1 with
all other bits cleared (%1000001).
8-7