HP 3000 III Series Manual page 78

System/CPU Overview
Table 2-6. Bounds Checks Summary
Check
Definition Mode
Program Transfer PB
~
E
S. PL
Pr ivileged, User
Program References
PB S.
E
~
PL User only
(e xcept moves)
Data Ref erences DL
~ E
S. S User only
Stack
Ov~rflow SM
>
Z
Pr i vileged, User
Stack Underflow SM
<
DB User only
I
E =
effective addres s of memory address
the ALU) and read onto the R-Bus and/or S-Bus (inputs to ALU) •
The ALU executes various functions (add, subtract, etc.) on the
R- and S-Bus inputs (with or without a shift) and outputs the
result to either of the CPU registers for transmission out of the
Central Processor Module or to the U-Bus for storage in one of
the internal registers. For a more detailed discussion of the
CPU logical components, refer to paragraph 2-75.
2-72. Pipelines
There are two pipelines in the CPU; a microcode pipeline and a
data pipeline. Basically, the microcode pipeline consists of the
Current Instruction Register (CIR), CMUX, Mapper, Look Up Table
(LUT) , VBUS MUX, ROM, RORl, and ROR2. See figure 2-20. The data
pipeline basically consists
ot
the Store Logic, various regis-
ters, R- and S-Bus Logic, ALU, Shifter, and Decimal Corrector.
2-73. DATA PIPELINE. In general, the data pipeline picks up two
operands via the R- and S-Bus Logic and R- and S-Bus Registers
(figure 2-20) and inputs them to the ALU where a mathematical
calculation can be performed. The result is then outputed to
either the Shifter or Decimal Corrector where it can be either
shifted (shift left 1, shift right 1, or swap bytes with or
without clearing either byte), or its decimal arithmetic cor-
rected. The final result is then put on the U-Bus and either
stored in anyone of the registers or input to the ALU a second
time for additional calculations.
To give the data time to propagate through the entire pipeline,
the data is stepped through in two steps. The first step is to
read the operands from the two source registers to the input
lines for the R- and S-Bus Registers. This is accomplished in
one 175-nanosecond clock cycle. rrhe second step is for the data
to go through the ALU, Shifter or Decimal Corrector, and Store
Logic and then be on the input to the selected store register.
This is accomplished by the next 17S-nanosecond clock cycle.
2-46