HP 3000 III Series Manual page 294

I/O Sy stern
Channel Bus rather than to the IOD lines of the lOP Bus.
When the Selector Channel (figure 7-19) receives a Request (REQ)
from the Device Controller, it sets the control logic to "ac-
tive". The Selector Channel then issues the Device Number Data
Base (DEVNO DB) to the Device Controller. The Device Controller
gates the DEVNO, left shifted by two, onto the SR (Data) lines of
the Selector Channel Bus. The DRTE address is then loaded into
the DEVNO DBV Register. The Selector Channel is now exclusively
reserved for that device. Only this Device Controller will re-
spond to Channel Service Out (CHANSO) from the Selector Channel.
The Selector Channel now reads the device number from the DEVNO
DB Register and requests a memory transfer by issuing a Read to
the Port Controller (figure 7-17). The Port Controller checks if
memory is ready and, when Enable (ENB) is present, sets the LSEL
flip-f lop. The LSEL signal is returned to the selector Channe 1
(figure 7-19), where it reads the DRTE address onto the peD lines
on the PC Bus. LSEL also reads out the TO, FROM, and MOP codes
in the Port Controller, thus effecting an address transmission to
memor y.
When memory returns the DRT contents, the Port Controller issues
STRB to the Selector Channel. Since the Selector Channel control
logic is expecting a DRT word, it loads the bus data into the I/O
Program Counter. The contents of the I/O Program Counter will
hereafter be used to address the individual locations of the I/O
program an~ no further DRT fetches are necessary. Program execu-
tion will .occur as a result of fetch and execute sequences.
7-50. FETCH SEQUENCE. Fetching an I/O program doubleword re-
quires two memory fetches. Unli ke the Mul tiplexer Channel which
examines the IOCW to determine what to do about the IOAW (fetch
it, store into ·it, or gate it out to the device controller) the
two memory fetches always occur. The different operations for the
various types of I/O orders are accomplished in the execute se-
quence. The fetch sequence begins with the selector Channel
reading out the contents of the I/O Program Counter and request-
ing a memory read. When the Port Controller has obtained trans-
mit priority, it returns LSEL, transmitting the I/O Program
Counter contents to memory as an address. (The Counter is incre-
mented immediately.)
When memory returns the IOCW from the addressed location, the
Port Controller issues STRB to the Selector Channel. The Selec-
tor Channel contorl logic, which is expecting the IOCW, loads the
word into the IOCW Active Register. Then the I/O Program Counter
is again read out with another memory transfer request. The Port
Controller transmits this address to memory and the I/O Program
Counter is again incremented. Then, when memory returns the IOAW
from the addressed location, the Selector Channel loads the word
into the IOAW Active Register. At this point the fetch sequence
is cornple te •
7-40