HP 3000 III Series Manual page 115

System Verification and Troubleshooting
Table 3-2. Maintenance Panel Switches and Lamps (Continued)
Use
-~------_.-
1
1
I·
._~
I
1
When enabled by the lOP SINGLE STEP EN-
1
ABLE/INHIBIT switch, the lOP executes
one step each time this switch is used.
lOP SINGLE
STEP EXECUTE
(sp r ing-re tur n
sw itch)
11
I-----T--- .. I
IPanell Panel Marking
1
1
Row
1 1 '
1 _ - 1 1 - __. ._
11 RESET CPU
(spr ing-retur n
sw itch)
The CPU and MCU are reset when this
switch is pressed. To avoid improperly
changing the contents of registers, the
switch should be pressed only when the
computer is halted.
11 RESET I/O
(spr ing-retur n
switch)
All I/O subsystems are reset when this
sw itch is pressed.
11 CLOCK EXT/INT
(bistable
switch)
At the INT position, this switch allows
the CPU to use the clock pulse generated
within the CPU. At the EXT position, the
switch selects a clock pulse produced by
an external pulse genera tor.
The external clock pulse must have the'
following characteristics:
Source impedance: 50 ohms or les s
Source must sink
up
to 60 mae
High level: +2.5V to +5.0V
Low level: O.OV to +0.4V
Maximum rise time: 10 nsec
Maximum fall time: 10 nsec
High time: 20 nsec to infinite time
Low time: 20 nsec to infinite time
Maximum frequency: 25.0 MHz
Minimum frequency: 0 Hz
To equal the internal clock-pulse rate,
the external clock-pulse frequency must
be 22.8571 MHz. This corresponds to a
period of 43.75 nsec, which, because of
a div ide-by-four action in the CPU, pro-
vides a l75-nsec computer clock cycle.
The external clock pulse is supplied to
a BNC-type connector on the CPU back-
plane. The connector is labeled EXT -
CLOCK. A 50- ohm termination impedance
is provided in the cPU.
3-15