HP 3000 III Series Manual page 318

Inte rr upt System
n. The starting address of the interrupt receiver code is ob-
tained from the STT entry pointed to by the external program
label in the DRT entry. The interrupt receiver code segment
number is placed in the Status Register. The P Register (14)
is set to this value and the CPU fetches the instruction at P
and begins executing the interrupt receiver code.
The following steps relate to figure 8-4 and list the actions oc-
curring if a second interrupt of higher priority is received
while processing the first interrupt. Assuming a still higher
priority, another interrupt could interrupt the second routine in
the same manner as descr ibed below. This example shows how sev-
eral levels of interrupts can be nested on the ICS. Since the
ICS is common to all external interrupts, no further switching of
environments is necessary for additional interrupts. This reduc-
es the interrupt response time. If, however, the second inter-
rupt did not occur before completing the processing of the first
interrupt, the sequence of operations would skip from this point
(step a) to step g. The CPU recognizes a second interrupt while
executing the interrupt receiver code for the first interrupt.
The CPU, therefore, again passes control to the Interrupt Hand-
ler. The sequence continues as follows:
a. The Interrupt Handler pushes into memory any TOS elements
that are in CPU registers, and pushes the usual six-word mar-
ker onto the ICS. The fifth and sixth words are the values
that are currently in the DB-Bank and DB Registers respec-
tively at the time of the interrupt.
b. The Q Register is updated to point at the Delta-Q word of the
new mar ker. The Del ta -Q value is the
n
umber of loca tions
back to the Delta-Q word of the previous marker.
J:\1o
te
Unlike the first interrupt, subsequent in-
terrupts do not store S into Q-6 at this
point since such action would overlay one
of the variables associated with the user
who was first interrupted.
c. The CPU obtains the device number from the Interrupt Address
Register in the lOP and calculates the address of the DRT
entry. DB is set to the DBI value in the third word of the
DRT entry.
d. The S Register is set to point at location Q+3 and the device
number is stored into this location. At this point, the ICS
is fUlly delim ited by registe r values and is ready for hand-
ling interrupt data. .
8-12