HP 3000 III Series Manual page 227

MCU/Main Memory Overview
receive a transmission because a memory operation is being initi-
ated, whereas high request assumes that the destination module is
expecting the transmission of data to complete a memorywrite
operation.) By this time, the MCU Encoder has encoded the appro-
priate memory opcode (MOP), which is now in the MOP Register.
The memory opcode is a two-bit code which tells memory what to do
when it receives bus data. There are three possible memory op-
codes: No Operation (NOP), Write (W), and Read (R). NEXT locks
the code in the MOP Register and sets the Next In Process (NIP)
flip-flop. Setting NIP opens the next instr uction re,gister so
that all CTL-Bus transmissions are gated to NIR until NIP is re-
set. NEXT also locks the TO Register which now contains the des-
tination module number.
The LREQ signal reads the contents of the TO Register into the
Ready Comparator which checks the Ready (ROY) line for the in-
tended destination to see if that module is ready to receive. If
not, nothing further happens until the the RDY line is true. The
output of the Ready Comparator, through a set of changeable jump-
ers, pulls the Enable (ENB) line low for this module number.
Since no module can transmit unless all ENB lines of higher pri-
ority modules are high, pUlling the ENB line low disables all
lower priority modules. Provided that no higher priority module
has pulled its ENB line low to this module ,(through a second set
of jumpers), and provided the I/O Processor is not requesting the
bus, the output of the Ready Comparator now sets the CPU Select
(SEL) flip-flop. The SEL signal reads out the ACOR contents to
the CTL Bus as well as TO and FROM module numbers and the memory
opcode. SEL also pulls the destination module's RDY line low for
one cycle so that other modules will not assume that the memory
module is ready before memory has a chance to pull the ROY line
low itself on the next cycle.
6-4. MEMORY RECEIVE AND TRANSMIT. The memory module's TO Cam-
para tOl' (figure 6-2) identifies the code on the TO
I
ines as its
own module number and se ts the Ready fl ip-f lop and Addres s
La
tch
flip-flop which locks the address word from the bus into the Ad-
dress Register and the FROM address into the From Register. The
Ready signal also keeps the module's ROY line pulled low (the CPU
had pulled it low temporarily in the preceding cycle) and, to-
gether with the decoded memory opcode, begins the read memory
cycle. The addressed memory location is read into the Read Data
Register. Meanwhile, on the next clock edge, the MCU begins the
process of requesting access to the bus by setting the Enable
flip-flop. (Since memory transmits only to modules that are ex-
pecting the transmission, only high requests are used.) The En-
able signal pulls its enable (ENB) line low to lower priority
modules and, provided no high priority module has pUlled low on
its ENB to this module, pets the Data Out flip-flop on the next
clock edge. The memory loca tion contents are in the Read Da ta
Register and the Data Out signal reads the contents out to the
CTL Bus. The Data Out signal also reads out the wired FROM code
and TO code (which is simply the saved FROM code, since transmis-
sion is back to the CPU).
6-3