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Inte rrupt System
a-u
Sequence of Operations
Figures 8-3
and 8-4 illustrate the
sequence
of operations
for
processing
external interrupts.
Basically, this discussion cov-
ers that
portion of the overall I/O
operation that
establishes
the interrupt
processing environment
on receipt of
an external
interrupt.
In previous figures, this corresponds to steps
(11)
and
(12)
in figure 7-5, and to steps (5), (6), and (7) in figure
8-2.
Figure 8-3 illustrates how control is transferred from the
point
of interrupt in a user's code
segment to the start of the inter-
rupt receiver code.
Also shown is the transfer of the
data do-
main from
the
current
user's
stack
to the interrupt
control
stack.
Figure 8-4 illustrates how a second inte rrupt is
handled
and
how exit is made from the interrupt routines.
The following
paragraphs descr ibe the sequence of operations, step by step.
It
should be
noted that
all operations
are
under control
of the
hardware-implemented Interrupt Handler until control is transfer-
red to the interrupt receiver code in software.
Initially, it is
assumed
that the current process is operating at point P in some
user's code when the
CPU recognizes an external interrupt.
The
CPU thereupon passes control to the Interrupt Handler.
a.
The first
action of the
Interrupt Handler
is to
push into
memory any
TOS elements of the current user's
data that are
in CPU registers (1, figure 8-3).
This takes
a
maximum of
four memory
cycles if all four registers are full.
Next, a
normal four-word stack marker is pushed onto the user's stack
followed by the value of the user's DB-Bank and the
absolute
value of DB that is currently in use. (DB may not necessarily
point to a
location within the user's stack,
such
as if
a
system intrinsic
using a split stack had been
called at the
time of the interrupt.)
This action
preserves
most of
the
user's environment;
the current value of S will be preserved
la te r ins te p f.
b.
The S-Bank Register
(2) is set to O.
(The ICS
is always in
Ba nk
0.)
c.
The Interrupt Handler now goes to location 5 and loads the QI
value into the Q Reg iste r
(3).
This points a t
the
Del ta
Q
location
of
the permanent Dispatcher marker.
(As explained
previously, this location contains a value of
0.)
d.
The contents of location 6 are fetched and the value of ZI is
loaded into the Z Register (4).
This establishes the
stack
limit for the ICS. (The ICS Flag in the CPXl Register is also
se
t.)
e.
The DL Register (5) is set to the limit value of %177777.
f.
The user's value of S relative to Stack DB
(a t QI-4)
is cal-
culated and stored in QI-6 (6).
8-9
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