HP 3000 III Series Manual page 72

System/CPU Overview
assumed "LOAD P-ll, X" instruction. The displacement (-11) is
added to the positive index of 5 and the final address is P-4.
The third example shows code indexing combined with indirect
addressing. In all cases, post- indexing is used; i.e., the
indirect addressing is accomplished first (either positive or
negative direction), and then indexing proceeds in a positive or
negative direction fram the indicated location. As shown in the
example for the "LOAD P+4, I,
X"
instruction, the displacement of
+4 points to the Indirect Gell at P+4. The contents of P+4 is a
self-relative address of 3 that points to P+7. However, indexing
adds 5 to this value and the final effective address becomes P+14
(octal) •
2-55. DATA INDEXING. The first example in figure 2-16 shows the
actions occur ing for an assumed "LOAD DB+4, X" instr uction • The
displacement (+4) points at DB+4 which is then modified by the
index of 5 to point at DB+ll. The second example shows the ac-
tions occur ing for an asumed "LOAD S-ll,
X"
instr uction wh ich is
similar to the actions occuring for the "LOAD P-ll, X" instruc-
tion discussed in paragraph 2-54. Since a positive index is
specified, indexing proceeds in a positive direction from the
location indicated by the displacement. The third example shows
data indexing combined with indirect addressing. Again, post-
indexing is used. The displacement (+4) points to the Indirect
Cell at Q+4 which contains the value 3. Since indirect addresses
for data are always DB+ relative, this points at location DB+3.
This is modified by the addition of the index 5 and the final
effective address becomes DB+lO (octal).
2-56. Byte Addressing
The Load Byte (LDB), Store Byte (STB), and five Move Instructions
(Section IV) use the byte addressing convention. Since the CPU
is not specifically organized as a byte processor, the byte ad-
dressing convention uses the contents of the X Register, an in-
direct cell, or a stack word to specify the desired byte. For
memory addressing (Load Byte and Store Byte instructions), the
displacement value remains a word displacement. The byte data
label in an indirect cell is an inflated value of two times the
word displacement fr am DB. The contents of the X Registe rand/or
an indirect cell indicate the desired byte in a byte array. For
Move instructions, one or two of the TOS locations give a PB+ or
DB+ relative byte index. The byte addressing range is therefore
restricted to 32K words; 15 bits for word addresses and one bit
for byte number. Four examples of byte addressing for memory
address instructions (LDB and STB) are shown in figure 2-17. (The
convention for the Move Instructions corresponds to the Direct,
Indexed example in figure 2-17. The difference is that the byte
index would be obtained from a IDS word rather than the
X
Re
g
i s te r • )
2-57. DIRECT BYTE ADDRESSING. For direct,
un
indexed byte ad-
dressing, the displacement value given in the instruction word is
str ictly a word displacement and only the left byte of each word
is addressable. As shown in figure 2-17, an "STB DB+7" instruc-
2-40