HP 3000 III Series Manual page 89

System/CPU Overview
2-97. TOS Registers. The TOS registers consist of eight 16-bit
registers designated TROR through TR3R and TROS through TR3S.
The two groups of registers always contain the same data (i.e.,
TROR
=
TROS, TRIR
=
TRIS, etc.). The registers contain up to
four of the top elements of the current data stack. The TOS
registers are read by R-Bus field codes RA, RB, RC, RD, and MREG
and by S-Bus field codes RA, RB, RC, RD, and QDWN as discussed in
Section
V.
The TOS registers are llooded by Store field codes RA,
RB, Re, RD, PUSH, and QUP as discussed in Section V.
2-98. Index Register
(X).
The Index Register (X Register) is a
16-bit register that contains the index word to be used by memory
reference instructions if indexing is specified. Certain other
instructions use the
X
Register for parameters or addresses.
(Refer to paragraph 2-48.) The X Register is read by R-Bus field
codes X and XC and loaded by Store field code X.
2-99. Stack Limit Register
(Z).
The Stack Limit Register
(Z
Register) is a 16-bit register that contains an absolute address
pointing to the top memory location available to the current data
stack. Al though there are 128 word loea tions above the stack
limit, they are reserved for stack markers in the event of·an
inter rupt. (Re fer to par ag raph 2-28. ) The
Z
Reg iste r is read by
R-Bus field code Z and loaded by Store field code Z.
2-100. Program Limit Register (PL). The Program Limit Register
(PL Register) is a 16-bit register that contains the absolute
address of the upper location of the current program segment.
(Refer to paragraphs 2-24 through 2-28.) rrhe PL Register is read
by R-Bus field code PL and leaded by Store field code PL.
2-101. Scratch Pad 0 Register (SPO). The SCratch Pad 0 Register
(SPO Register.) is a 16-bi t register that is used by the CPU to
store partial results during various CPU routines and as address-
es during memory transfers. The SPO Register is read by R-Bus
field code SPO and loaded by Store field codes SPO and BSPO.
2-102. Scratch Pad 1 Register (SPl). The SCratch Pad 1 Register
(SPI Register) is a 16-bit register that is used by the CPU to
store partial results during various microprogram routines. The
SPI Register can be left shifted and provides serial
da~a
input
to bit 15 and output from bit O. The SPI Register is read by
R-Bus field code SPl, loaded by Store field code SPl, and shifted
by Function field codes CTSD, DVSB, and QASL. In addition, the
SPI Register can be read onto the S-Bus by S-Bus field code SPI
(code is not the same as R-Bus field code SPl).
2-103. Stack :tegister
(SR).
The Stack Register (SR Register) is
a 3-bit register counter that provides the number of TOS regist-
ers that are currently in use. The SR Register works in con-
junction with the Namer Register to 110ea te and access any of the
t<:p four elements of the data stack. (Refer to paragraph 2-21.)
The SR Register is read by R-Bus field cede SR and modified by
Store field code PUSH and Special field codes INSR, DCSR, paPA,
CLSR, and POP.
2-57