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System/CPU Overview
2-87.
S-Bus Field Decoder (S).
The S-Bus Field Decoder (bits
0
through 4)
selects one
of 32 registers or
sets of Ijnes
to be
loaded into the S-Bus Register.
S-Bus field code definitions are
contained in section
V.
2-88.
Store Field Decoder (STORE). The Store Field Decoder (-bits
5 through 9)
selects one of the Store
Logic registers
or other
destinations
outside the CPU for the
V-Bus
data.
Store field
code definitions are contained in Section
~.
2-89.
Function Field Decoder
(FCN).
The Function Field
Decoder
(bits 10 through 14)
specifies the
function to be
performed by
the ALU on the two operands in the R- and S-Bus Register s.
F unc-
tion field code definitions are contained in section V.
2-90.
Skip Field Decoder
(SKIP). The Skip Field Decoder (bits 15
through 19) determines which
condition will be tested for a pos-
sible skip.
If the condition is met,
ROR2 will
execute a
Nap,
effectively skipping
one microinstruction word.
The Skip field
also specifies
the conditions under which a JMP or
JSB will
be
executed if
coded in the microinstruction.
Other signals, such
as NEXT
which calls the next instruction from
memory,
are also
decoded
from the
Skip field.
Skip field code
definitions are
contained in section V.
2-91.
Shift Field Decoder (SHIFT). The Shift Field Decoder (bits
20 through 22)
specifies how the T-Bus data will be shifted.
In
addition, the Shift field generates the SCratch Pad 1 and Scratch
Pad 3 Register shift
signals used in conj unction with
the Func-
tion field.
The Shift field code
definitions are contained in
Section V.
2-92. Special Field Decoder (SP). The Special Field Decoder (bits
23 thr"ough 27) performs varied operations such as generating mem-
ory
operation code signals and
the POP
signal.
Special
field
code definitions are contained in Section
~.
2-93.
MCU Cption Field Decoder
(MCU).
The MCU Option Field
De-
coder
(bits
23 through
27)
uses the same bits
as the Special
Field Decoder.
The Special Field Decoder is disabled and the MCU
Option Field
Decoder is enabled when
executing
an
S-Bus field
code
RBR or a Store field code BUS, BSPO, BSPl, or SBR.
The MCU
Option Field
Decoder ini tiates transfer s to or
from memory
and
transfers from ACOR to the Operand,
Next Instruction, or Command
Registers via the CTL Bus.
MeU Option field code definitions are
contained in section V.
2-94.
R-Bus Field Decoder (R).
The R-Bus Field Decoder (bits 28
through 31)
selects one
of 16 registers
or sets
of lines
for
loading
into the
R-Bus Register.
R-Bus field code definitions
are contained in Section V.
2-55
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