HP 3000 III Series Manual page 91

System/CPU Overview
The clocking interval is 1.001 ms. The maximum range of the
clock before rollover is approximately 65.5 seconds.
2-112. Program Counter Register (P). The Program Counter Regis-
ter (P Register) is a l6-bit register that contains the absolute
address of the next program instruction to be fetched from mem-
ory. During execution of Skip field code NEXT, the P Register and
PB-Bank Register are used to select a memory module and prefetch
the instruction following the one which is about to be executed.
(Re fer top a rag rap hs 2- 21 th r oug h 2- 28 . ) The P Re g i s te r i s rea d
by S-Bus field code P and loaded by Store field code P.
2-113. Operand Register (OPND). The Operand Register (OPND
Register is a l6-bit register that provides storage for data read
from memory by the cpu. The OPND Register is loaded by an OPINP
signal from the Operand In Process (OPINP) flip-flop in the Mcn
operation decoder as a result of MCU options OPND, RNWA, RWA, and
RWAN. The OPND Register is read by an RDOPND signal from the
S-Bus Decoder as a resul t of S-Bus field code OPND. When the CPU
freezes for an operand, the operand from memory goes directly to
the S-Bus Logic as well as into the OPND Register. It is then
loaded into the S-Bus Register to await CPU operation.
2-114. Status Register (STA). The Status Register (STA Register)
is a 16-bit register that indicates the current status of the CPU
hardware. (The status word format is discussed in paragraph 2-
45.) The STA Register is read by S-Bus field code STA and
loaded by Store field code STA. Status bits are also affected by
Function field codes CADO, SUBO, INCO, and ADDO; and by Special
field codes CCB, SCRY, CCRY, POPA, SOV, CLO, CCZ, CCL, CCG, CCE,
and CCA.
2-115. Counter Register (CN'rR). The Counter Register (CNTR
Register is a 6-bit register that is used as a repeat counter by
the cpu. The two's complement of the desired count is loaded into
the CNTR Register and the register is then incremented for each
repeated execution until it contains all ones as indicated by a
CTRM code from the Skip field. The CNTR Register is affected or
referenced by S-Bus field codes CTRI and CTRH, Function field
code REPN, Store field codes CTRL and CTRH, Special field code
INCT, and Skip field code CTRM. Additionally, the C~TR Register
saves the contents of the SR Register when the CPU is put in the
Hal t MJde. Therefore, after a hal t has occured, the CNTR Register
can be displayed to show what the contents of the SR Register was
just prior to the halt.
2-116. OVERFLOW FLIP-FLOP (OVF'L). The Overflow flip-f lop con-
trols the status word overflow bit (bit 4) and stores the state
of the Overflow signal from the ALU when the OFCENB signal is
true. The Overflow flip-flop is set and cleared by Special field
codes SOV and CLO respectively. Refer to paragraph 2-45.
2-59