HP 3000 III Series Manual page 286

I/O System
The Device Controller, for a DRT fetch, reads out its device num-
ber (DEVNO) onto the IOD lines. Instead of being read onto the
eight least significant lines of the bus (8 through 15), the num-
beris read onto lines 6 through
13,
which is left-shifted by two
bits. This effectively mUltiplies the number value by four, thus
automatically providing the correct address for that device's DRT
entry. (Remember that each device uses four locations in the
DRT.) Simultaneously, the Mlltiplexer Channel is returning an Sl
response to the lOP along with an 10CMD which tells the lOP to
accept the address existing on the IOD lines and that a DRT fetch
fr om that address is required.
The lOP then proceeds to fetch the DR'r entry. (See figures 6-1
and 7-10.) The lOP issues an IOLRQ to its MCU with an appropriate
MOP to read memory. When select occurs, the address is transmit-
ted to memory. When memory returns the DRT entry contents, I/O
Strobe (IOSTRB) loads the word into the lOP Data Out Iegister.
The lOP Data Out contents are then read out onto the IOD lines
and SO is issued. Upon receipt of SO, the Multiplexer Channel
loads the DRT word into the Address RAM, restores the Order Reg-
ister contents into the Order RAM, and sets the State RAM to the
condition required for an I/O program word fetch. Meanwhile, the
lOP transfers its copy of the DRT word from the Data Output Reg-
ister to the Data Input Iegister, increments it by two, and sends
it back to the DR!' in memory. (This is an anticipatory move, as
the Address RAM presently conta ins the des ired address for the
next operation; the incremented address in the DRT will not be
used un til the next DRr fe tch.)
7-36. I/O PROGRAM WORD TRANSFERS. Each I/O program word consists
of two words in Bank 0 of Miin Memory; the IOCW and the 10AW".
Therefore, two memory transfers are required. The first transfer
is to fetch the IOCW. Depending on the order that the 10CW con-
tains, the second transfer may be either a fetch or a store.
7-37. 10CW Fetch. The SR fl ip-f lop in the Device Controller is
still set from the previous procedure (DRT Fetch, paragraph 7-4) ,
so HSREQ is still present at the lOP. The lOP therefore issues a
new DATA POLL. The SR Latch in the Multiplexer Channel, which
had reset on the trailing edge of the previous SO, has become set
again since the SR input was still present at the next clock.
Thus DATA POLL is stopped from further propagation, and the
Transfer/Control Logic is enabled again.
The contents of the Address RAM location are loaded into the
State, Address, and Order Registers. The state specifies an 10CW
fetch, so the transfer logic reads out the contents of the Ad-'
dress Register and issues Sl and the 10CMD "transfer from memory"
to the lOP. The address now on the 10D lines is the word pre-
viously fetched from the DRT, indicating the address of the I/O
progr am word. The lOP issues an 10LRQ to the MCU. When pr ior i ty
allows, the MCU transmits the address to memory. When memory
re turns the 10CW, IOSTRB load s this word into the lOP Da ta Out
Register in the lOP. The lOP then reads the word out to the 10D
lines and issues SO.
7-32