HP 3000 III Series Manual page 319

Interrupt System
e. The external program label for the interrupt receiver code is
fetched from the second word of the DRT entry. The starting
address of the interrupt receiver code is obtained from the
STT entry pointed to by the external program label. The P
Register is set to this value and the CPU fetches the in-
struction at P and begins executing the interrupt receiver
code.
f. Assuming there are no other higher priority interrupts, the
interrupt routine for the second device runs to completion
and then exits using the IXIT instruction. The exit, as us-
ual, is made via the stack marker. The return address is
obtained from the stack marker, the
Q
Register is restored
back to the previous setting (using the Delta-Q value from
the stack marker), pointing to the Delta-Q word of the Dis-
patcher marker. The S Register is moved back to the location
just preceding the second stack marker. One of the actions
of the IXIT instruction is to issue a Reset Interrupt command
to the interrupting device controller which clears the inter-
rupt active condition and unblocks the interrupt poll line to
lower priority devices.
g. The interrupt receiver code for the first interrupt now runs
to completion and an exit is made, usually back to the user
process. Again, the IXIT instruction issues a Reset Inter-
rupt command to the device controller. This completes the
sequence of operations.
If an external interrupt should occur while the Dispatcher is ex-
ecuting, the interrupt is treated in a slightly different way.
If the CPU recognizes an interrupt while the Dispatcher Flag is
set, the sequence effectively repeats steps b through g above
with the added actions that, in step d, bit 0 of Delta Q is set
to 1 (indicating a Dispatcher interrupt) and the Dispatcher Flag
is cleared.
8-12. INTERNAL INTERRUPT PROCESSING
As listed in table 8-1, there are 35 internal interrupts includ-
ing 14 user traps. These 35 interrupts are processed by the seg-
ment whose CST entry number is 1. Each interrupt has an entry in
the Segment Transfer Table (STT) which points to the start of the
code to process the interrupt. The user-related traps"all share
the same STT entry and the parameter value determines the proces-
sing to be performed. When internal interrupts are being proces-
sed, all external interrupts are disabled. Internal interrupts
therefore have higher priority. Among internal interrupts, how-
ever, there is no priority structure (except in the case of sim-
ultaneous interrupts); any internal interrupt may interrupt the
processing of any other. If multiple interrupts occur simultan-
eously, they stack their markers in the following order and are
therefore, serviced in the reverse order; integer overflow, sys-
tem parity error, memory address parity error, data parity error,
non-responding module, bounds violation, illegal address, module
interrupt, external interrupt, and power fail. In all cases, the
8-13