HP 3000 III Series Manual page 299

I/O System
turns LSEL, the address from the I/O Program Counter is sent to
memory. When HREQ sets the HSEL flip-flop, the word count from
the Residue Register is sent to memory. This stores the residue
in the IOAW location.
7-59. Write. The Write order causes a block of data to be
transferred form memory to the device. The block size in words
is specified in two's complement form by the word count (IOCW
bits 4 through 15) and the absolute starting address of the block
in memory is specified by the IOAW. While the block transfer in
progress, there are two separate, simultaneous operations taking
place; the memory-to-channel transfer and the channel-to-device
transfer. To begin the Write execute sequence, the Selector
Channel issues CHANSO to the controller and, when the controller
returns CHAN ACK,. both the Selector Channel and the controller
are set to the out-transfer condition to enable data transfers.
Meanwhile, the Selector Channel proceeds with a memory fetch and
will attempt to keep both Output Buffers full. The control logic
for the A and B Output Buffers ensures that data is transmitted
to the device in the same sequence as it was fetched from memory.
To accomplish a memory fetch, the Selector Channel enables the
IOAW Active Register for use as a memory address and sends a Read
Request and the Bank Register as a TO address to the Port Con-
troller. When the port returns LSEL, the IOAW is gated onto the
bus as an address to memory and the IOAW is incremented to point
to the next data location. When the port returns STRB, the data
on the bus from memory is loaded into an empty Output Buffer.
The preceding operation in this paragraph repeats until the Write
order completes by either a DEV END or word count rollover.
When the controller is ready to accept a data word from the chan-
nel, it sends CHAN SR. The channel issues CHANSO and P WRITE STB
and gates Output Buffer A or B onto the channel Data lines. The
control~er returns CHAN ACK causing the channel to remove P WRITE
STB, increment the word count, and remove CHANSO in that order.
The Device Controller uses the removal of P WRITE STB to latch
the data word from the channel Data lines. The previous transfer
sequence in this paragraph repeats for each data word sent to the
Device Controller until the Device Controller asserts DEV END to
prematurely terminate the block or until the word count rolls
over. In either case, the Selector Cllannel sends EOT (End of
Transfer) to the controller and, if not data chaining, . clears the
out-transfer condition. To resume program execution, a new CHAN
SR from the controller is required by the Selector Channel.
If the data chaining bit is true, (IOCW bit 0) the next order
pair will have been prefetched when possible during the block
transfer. When the Write order completes, the pre-fetched order
pair will be transferred from the IOCW/IOAW buffers to the Active
Registers without the need for a normal fetch sequence. Data
output to the controller can thus continue for the next block
with minimum interruption. If the data chaining bit is not set,
termination of the Write order will be followed by a normal fetch
sequence.
7-45