HP 3000 III Series Manual page 289

I/O Sys tern
7-43. Output Transfer. When memory returns a data word, 10STRB
loads the word into the lOP Data Out Register. The lOP then
reads the contents of this register out to the 100 lines and is-
sues SO. Upon receipt of SO, the Multiplexer Channel issues a
command to the Device Controller via the MUltiplexer Channel Bus
telling the Device Controller to load the word on the bus into
its Data Out Buffer. The Device Controller returns Sl to the lOP
and proceeds to output the word to the device. Simultaneously,
the Multiplexer Channel restores the contents of the State, Ad-
dress, and Order Registers into the RAM location, and the output
data transfer is complete. Some other operation for another de-
vice could be interleaved here. Otherwise, the entire data
transfer procedure repeats.
7-44. Input Transfer. As the input data transfer procedure be-
gins, memory is expecting the data. The procedure begins when
the lOP sends SO to the Multiplexer Channel to ask for data.
Upon receipt of SO, the Multiplexer Channel issues a command to
the Device Controller via the Multiplexer Channel Bus, telling
the Device Controller to read the contents of its Data In Buffer
out to the 10D lines. When the Device Controller does this, it
also sends an Sl response which causes the lOP to load the data
into its Memory Data Input Register. The lOP then issues 10HRQ
to its MCU with a Write MOP, causing a data transmission to mem-
ory via the MCU Bus. Simultaneously, the Multiplexer Channel
restores the contents of the State, Address, Auxiliary, and Order
Registers into the RAM location, and the input data transfer is
complete. Some other operation for another device could be in-
terleaved here. Otherwise, the entire data transfer procedure
repeats.
7-45. End Of Transfer By Word Count. If the word count rolls
over while incrementing (during the address transfer sequence),
then in the data transfer sequence the Multiplexer Channel will
issue a command which will reset the in-transfer or out-transfer
condition in the Device Controller. Also, an End-of-Transfer
(EOT) signal accompanies the last command from the MUltiplexer
Channel to read or write. The Device Controller logic will there-
fore not transfer any more data to or from the device. It will,
however, issue one more SR. In the Multiplexer Channel, the
transfer logic sets the next state to DR!' fetch, when restoring
the RAMS at the end of the final data transfer. When the Multi-
plexer Channe
I
re ce ives the SR fr om the Dev ice Contr oller and
when priority conditions are satisfied, a new DRT fetch procedure
will begin. This advances the I/O program to the next IOCW.
7-46. End Of Transfer By Device. On termination of a transfer
by a device, the Device Controller issues an SR to the Multiplex-
er Channel. The MUltiplexer Channel responds with CHAN SO. The
Device Controller returns a Device End signal that causes the
MUltiplexer Channel to initiate a DRT fetch, thus advancing the
I/O program to the next IOCW.
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