Tos Namer Relationships - HP 3000 III Series Manual

System/CPU Overview
2-95. PROCESSOR REGISTERS. Except for the Operand (OPND), I/O
Address, I/O Direct Data In, CPXl, and CPX2 Registers, the pro-
cessor registers can be selectively loaded from the U-Bus and
selectively read into the R- and/or S-Bus Registers. The proces=
sor registers are illustrated in similar readout groups in figure
2-20. For example, the X, Z, PL, SPO, and SR Registers can be
read out onl y to the R-Bus Reg ister. The SPI Reg ister ca n be
read out to either the R- and/or S-Bus Registers. Similarily,
the PB, DL, SM, DB, Q, SP2, SP3, PCLOCK, and OPND Registers can
be read out onl y to the S-Bus
Re
gis ter .
De
s cr ipt ions of the i
n-
dividual processor registers, including the renamer logic, are
contained in paragraphs 2-96 through 2-115. In addition, the
actions of many of the processor registers in an operating envi-
ronment are discussed in paragraphs 2-16 through 2-70.
2-96. Renamer Logic. The renamer logic consists the Namer, Adder,
three Mappers, four TOS registers (TRO through TR3) , and the
SR Register. These components are designated as the TOS register
renamer, or simply, the renamer. The renamer permits fast access
to the TOS elements by renaming the registers when stack elements
are added or deleted (rather than transferring data from register
to register). The ROM microprograms know TRO through TR3 only by
the names
RA
(top),
RB,
RC, and
RD.
The narner includes a 2 -bi t
Namer Register that tells the Mappers which of the four TOB reg-
isters (TRO through TR3) is RA, RB, RC, and
RD
as listed in table
2-7. ,The Namer Register is decremented each time a stack element
is added (PUSH) and incremented each time a stack element is de-
leted (POP). To keep track of how many elements are in the TRO
through TR3 registers, the 3-bit SR Register is incremented by
PUSH and decremented by POP in step with the Namer Register.
When the SR Register count is zero, there are no elements in the
TRO through rrR3 registers. This would indica te to a ROM micro-
program not to look for the TOB in the CPU and that one or more
memory fetches may be required. The Adder combines the outputs
of the Namer Register, SR Register, and
Be
ratch Pad 1 Reg ister
(SPl) and generates the TNAME signals (bits 0 and 1) for the
Mappers. (Refer to table 2-7.) The Mappers use the TNAME code to
control access to the TOB registers (TRO through TR3). The
TNAME
code specifies which of the TOS registers is
RA,
RB, RC, and
RD
as listed in table 2-7.
Table 2-7. TOS Namer Relationships
1----------------------------------
I
TNAME Code
=
00 01 10 11
I
I
RA
=
TRO TRI TR2 TR3
I
I
RB = TRI TR2 TR3 TRO
I
I
RC
=
TR2 TR3 TRO TRI
I
I
RD
=
TR3 TRO TRI TR2
I
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2-56