HP 3000 III Series Manual page 324

Interrupt System
tine software if it is desired to trace exits). In either case,
if the bit tested is 1, the trace routine in entered. For PCAL's
and external interrupts, another marker is stacked first which is
used by the EXIT from the trace routine. For EXIT and IXIT, no
marker is stacked; hence, bit
a
of the return address of the last
marker stacked (prior to EXITing from trace) must be cleared by
software in the trace routine. Otherwise, an infinite trace loop
could occur. Tracing segment 1 results in a system halt. Trac-
ing external interrupts or the Dispatcher requires special soft-
ware in the trace routine due to the differences in EXIT and
IXIT.
8-45. STT ENTRY UNCALLABLE. The uncallable bit in a local label
(or in PL if the STT number is 0) is set to 1. This label is
referenced by a PCAL from another segment. This trap does not
stack a new marker.
8-46. ABSENT DATA SEGMENT. The absence bit in the DST entry
for the referenced segment is set to 1.
The Power
On
routine is entered either by an
turn-on or by an automatic restart following a
when automatic restart is enabled by a panel-
computer will halt on restoration of power if auto-
is disabled.) Assuming that automatic restart is
Power
On
routine will set up the software environ-
control to the operating system.
8-47. POWER ON.
inte rnal power
powe r fa ilure
sw itch. (The
matic restart
enabled, the
ment and pass
8-48. COLD LOAD. Pressing the LOAD switch while simultaneously
pressing the ENABLE switch causes the CPU to start its cold-load
microprogram which begins by reading the operator-set switches on
the panel. The switches will have been set to indicate the cold
load device number and an 8-bit control byte. The microprogram
generates an eight-word I/O program beginning at the DRT entry
locations for the specified device and then'issues an SIO in-
struction to that device and goes into a waiting loop to wait for
an external interrupt from that device. Meanwhile the lOP causes
the device controller to begin executing the eight-word I/O pro-
gram. This program reads in a 32-word bootstrap loader (a larger
program) which in turn reads in still larger blocks (e.g., 128
words) which eventually accomplish the loading of all required
fixed memory locations. This includes overlaying the previously
used DRT locations with normal DRT entries. Finally, the I/O
program causes the device controller to generate the external
interrupt that the CPU has been waiting for, and ends. The CPU
then proceeds to initialize the registers for execution of code
segment 1, with the ICS as the data danain. The Status Register
is set to 100001 (octal) to indicate privileged mode, and code
se gment 1. Then the CPU hal ts • When RUN is pres sed, the cold-
load routine in segment 1 will execute, setting up the operating
conditions for the operating system (software tables, linkages,
etc.). Once this is complete, the system is in full operation.
8-18