HP 3000 III Series Manual page 112

System Verification and Troubleshooting
Table 3-2. Maintenance Panel Switches and Lamps (Continued)
- - - 1 - - --"_._-
------1----·--------·-·-----------'-·-------·--_. . - -,
Panel
I
Panel Marking
I
Use
I
Row
I I I
I I I
----. -----,--------. ------.--------.-,----.---.--.----. .
- -.----.-~----"
I
7 ROM 0 through Displays the contents of the ROM output
I
31 (lamps) registers. Lamps
(0:4)
and (28:31) dis-I
play RORI. Lamps (5:27) display ROR2.
I
I
7
8
9
10
10
B12, B13
(lamps)
V
BUS 2
through 15
(lamps)
V BUS COMP ARE
REGISTER 0
through 15
(bi stable
sw itches)
B12, B13 (bi-
stable
sw itches)
V BUS JUMP
REGISTER 2
through 15
Display two MSB bank bits.
Display the address of the ROM data cur-
rently being accessed. Since the ROM is
two levels removed from the actual mic-
roinstruction being executed out of
ROR2, the address is normally two ahead
of the address being executed.
These switches specify the microprogram
address at which a V TRIG pulse will be
supplied. (The pulse is available at
test point E3 at the front of the MPI
PCA. It is also available at J3, pin 3
on the MPI PCA.)
These switches also specify a micropro-
gram jump address or halt address when
the V BUS COMPARE ENABLE/INHIBIT switch
is a tENABLE.
The V TRIG pulse or breakpoint halt
takes place at the completion of a par-
ticular clock cycle. To bring about the
effect at the desired clock cycle, the
microinstruction address set into the
V BUS COMPARE REGISTER switches should
be as follows:
Address +1 for completion of execution
of the R-Bus and S-Bus field s.
Address +2 for completion of execution
of the remaining microinstruction
fie Ids.
Used to set bank bi ts B12 and B13.
These switches specify the jump target
for:
3-12