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MODULE CONTROL UNIT! _
MAIN MEMORY OVERVIEW
I VI
I
This section
contains principles of operation and
servicing in-
formation for the computer system's Module Control Unit (MCU) and
Ma in Memory.
6-1 MCU OPERATIONS
As previously
discussed in paragraph 2-15,
each computer module
gains
access to the CTL Bus through its MCU.
For any given mod-
ule, the MCU may be located on a single
dedicated PCA,
distrib-
uted on
multiple PCA's,
or located
on a small part
of a
PCA.
Whatever its
physical
configuration
may
be however,
each MCU
performs the
same function of interfacing its
associated module
with all othe r
modules connected to the CTL
Bus.
Al though the
following discussion
of MCU operations
is specifically
for the
Central Processor Module MCU and Main Memory's MCU logic circuit,
it is
representative
of any
of the
other MCU
logic circuits.
Since the purpose of the MCU is to control CTL-Bus transmissions,
its operations
will be
discussed
dynamically by
following the
sequence of logical operations involved for each of the different
types of CTL-Bus transmissions between the CPU and
memory.
(For
information
concerning the MCU's operations with the I/O Proces-
sor, refer to Section VII.)
6-2. Fetch Next Instruction Operations
The operations
involved in order
to fetch
an instruction
from
memory consist of three major steps.
a.
The CPU transmits
the address of an instruction word to mem-
ory and tells memory what to do with that address.
b.
Memory receives
the address,
reads the contents
of the ad-
dressed location, and transmits the contents back to the CPU.
c.
The CPU
receives the instruction word and loads it
into the
NI R.
6-3.
CPU ADDRESS TRANSMIT.
When a
NEXT instruction
is decoded
from
the ROM Skip field, a NEXT signal loads the contents of the
P Register
(address of instruction to be fetched) into the
ACOR
Register.
(See figure 2-20.} NEXT also transfers the contents of
the NIR
into the CIR.
The CPU executes
the CIR contents.
The
objective is to
refill NIR while the
CIR
instruction
is being
executed so as
to implement the CPU instruction
look-ahead fea-
ture.
Assuming that the transmission may proceed, NEXT sets the
CPU Low Request
(LREQ) flip-flop
(figure 6-1) in the MCU.
(The
difference
between low request and high
request is that low re-
quest always che cks to see if the destination module is ready
to
6-1
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