HP 3000 III Series Manual page 287

I/O System
Upon receipt of SO, the Multiplexer Channel loads the IOCW into
the Order RAM. If the order is Control, the Multiplexer Channel
issues a command through the Multiplexer Channel Bus so that the
Device Controller will also load the IOCW into its Control Reg-
ister. The contents of the Address Register/Counter is incre-
mented by one and restored in the Address RAM. The next state,
fetch or store IOAW, is stored in the State RAM.
The next operation, transfer of the IOAW, begins the same way for
each of the orders. That is, SR to the Multiplexer Channel
causes a HSREQ to be sent to the lOP. The lOP returns a DATA
POLL which enables the Multiplexer Channel to load the addressed
RAM location into the State, Address, and Order Registers. Ac-
tion after this point varies depending on the order that the IOCW
contains.
7-38. IOAW Fetch. The Read, Write, Jump, Control, and Interrupt
orders each cause an IOAW fetch. However, the action taken upon
receipt of the IOAW is different in each case. ,The IOAW fetch
begins by reading the contents of the Address Register (incre-
mented on the trailing edge of DATA POLL in the IOCW fetch pro-
cedure) to the laD lines. The Multiplexer Channel also issues SI
and the IOCMD "transfer from memory" to the lOP. The lOP issues
IOLRQ with MOP to its MCU to request a memory read. When memory
returns the contents of the address location, IOSTRB loads it
into the lOP Data Out Register. The lOP then reads the contents
of the lOP Data Out Register to the laD lines and issues SO. For
Read, Write, Interrupt, and Jump orders, the Multiplexer Channel
will store the word (IOAW) into the Address RAM. For a Control
order, the Multiplexer Channel issues a command via the Multi-
plexer Channel Bus to tell the Device Controller to load the word
into its Control Register. For an Interrupt order, the fetched
information is loaded into the Address RAM but is disregarded.
For Read', Write, and Conditional Jump, a command is sent to the
Device Controller to specify conditions for the next action. For
Read, the in-transfer condition is set. For Write, the out-
transfer condition is set. For Conditional Jump, the Device Con-
troller is given the choice of setting or not setting the "j ump
met" cond i tion. If "j ump met" is tr ue in the next DRT fe tch se-
quence (or if an unconditional jump was given), a store operation
(instead of fetch) will occur. That is, the Multiplexer Channel
will cause the contents of the Address Register to be sent to the
lOP which will increment the value by two before storing in the
DRT. (The Address RAM already contains the correct jump address,
50
a DR!' fe tch is not neces sary.)
7-39. IOAW Store. The Sense, End, and Return Residue orders each
cause an IOAW store operation. This operation begins as the Mul-
tiplexer Channel reads the incremented contents of the Address
Register out to the laD lines and issues SI with a "transfer-to-
memory" IOCMD. The lOP loads this address into its Memory Ad-
dress Register (MAR) and issues IOLRQ to its MCU with a Clear/
Write MOP. The insuing CTL Bus transmission prepares memory for
receiving data. Simultaneously, the lOP has issued SO to the
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