HP 3000 III Series Manual page 63

System/CPU Overview
specifies whether the displacement is
+
(bit 7
=
0) or - (bit 7
=
1) relative to P.
2-44. MEMORY ADDRESS. Bits 0 through 3 encode the specific mem-
ory address. Bits 6 through 15 give both an addressing mode and
a displacement. (Refer to paragr aph 2 -48. ) Bi t 5 is used to
specify direct or indirect addressing (1
=
indirect, 0
=
direct).
Bit 4 is used to specify indexing (1
=
indexing), if desired. If
both indirect addressing and indexing are specified, post-index-
ing (paragraph 2-54) will occur.
2-45. Status Word Format
There is a status word for each code segment in the system. At
all times, the status word associated with a given process indi-
cates the machine status following the execution of the most re-
cent instruction in that segment. The status for the currently
executing segment is resident in the STA Register and is con-
stantly being updated as each instruction is executed. For seg-
ments that are not current (suspended by either an interrupt or
procedure call), the status word exists in a stack marker in a
data stack as discussed in paragraph 2-28. As shown in figure
2-6, status word bits 8 through 15 indicate the segment number of
the currently executing code segment (when the particular status
word is resident in the STA Register). Therefore, when a status
word is pushed into a stack marker by an interrupt or procedure
call, bits 8 through 15 identify the segment that is to be re-
turned to when execution is later resumed. The following des-
criptions of the status bits assume that the status word under
discussion is resident in the STA Register. All references to
"cur rent" cond it ions can also be infer red as "then cur rent" con-
ditions in the case of suspended segments or procedures.
Bit 0 is used to indicate whether the current segment is running
in privileged mode (bit 0
=
1) or user mode (bit 0
=
0). (Refer
to paragraph 2-47.) The state of this bit cannot be changed by
machine instructions while resident in the STA Register except in
privileged mode. (The PCAL, IXIT, and EXIT instructions include
checks to prevent illegal mode changes by al tering the noncurrent
sta tus mode bi ts.)
Bit 1 is used to enable or disable external interrupts. This bit
cannot be changed in user mode while current and the EXIT in-
struction invokes a trap if a non-privileged user illegally al-
ters the bit while non-current. The state of bit 1 can only be
changed in privileged mode.
Bit 2 is used to enable or disable user traps. The state of this
bit can be changed in any mode while current or non~urrent with
a SETR instruction. (The state of this bit is not affected by the
EXIT instruction.)
2-31