Xilinx VC7203 User Manual page 57

Virtex-7 fpga gtx transceiver characterization board
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NET
CM_CTRL_20
NET
CM_CTRL_21
NET
CM_CTRL_22
NET
CM_CTRL_23
NET
CM_RST
NET
IO_L17N_T2_38
NET
IO_L18P_T2_38
NET
IO_L18N_T2_38
NET
IO_L19P_T3_38
NET
IO_L19N_T3_VREF_38
NET
IO_L20P_T3_38
NET
IO_L20N_T3_38
NET
IO_L21P_T3_DQS_38
NET
IO_L21N_T3_DQS_38
NET
IO_L22P_T3_38
NET
IO_L22N_T3_38
NET
IO_L23P_T3_38
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IO_L23N_T3_38
NET
IO_L24P_T3_38
NET
IO_L24N_T3_38
NET
IO_25_VRP_38
NET
IO_0_VRN_39
NET
FMC3_HA11_P
NET
FMC3_HA11_N
NET
FMC3_HA12_P
NET
FMC3_HA12_N
NET
FMC3_HA13_P
NET
FMC3_HA13_N
NET
FMC3_HA14_P
NET
FMC3_HA14_N
NET
FMC3_HA15_P
NET
FMC3_HA15_N
NET
CM_LVDS1_P
NET
CM_LVDS1_N
NET
FMC3_HB01_P
NET
FMC3_HB01_N
NET
FMC3_HB02_P
NET
FMC3_HB02_N
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FMC3_HB03_P
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FMC3_HB03_N
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FMC3_HB04_P
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FMC3_HB04_N
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FMC3_HB06_CC_P
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FMC3_HB06_CC_N
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FMC3_HB00_CC_P
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FMC3_HB00_CC_N
NET
FMC3_CLK2_BIDIR_P
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FMC3_CLK2_BIDIR_N
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FMC3_CLK3_BIDIR_P
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FMC3_CLK3_BIDIR_N
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FMC3_HB05_P
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FMC3_HB05_N
NET
FMC3_HB07_P
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FMC3_HB07_N
NET
FMC3_HB08_P
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FMC3_HB08_N
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FMC3_HB09_P
NET
FMC3_HB09_N
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CM_LVDS2_P
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CM_LVDS2_N
NET
FMC3_HB10_P
NET
FMC3_HB10_N
NET
FMC3_HB11_P
NET
FMC3_HB11_N
NET
FMC3_HB12_P
NET
FMC3_HB12_N
NET
FMC3_HB13_P
NET
FMC3_HB13_N
NET
FMC3_HB14_P
NET
FMC3_HB14_N
NET
IO_25_VRP_39
NET
111_TX3_P
NET
111_RX3_P
NET
111_TX3_N
NET
111_RX3_N
NET
111_TX2_P
NET
111_RX2_P
NET
111_TX2_N
NET
111_REFCLK0_P
NET
111_RX2_N
NET
111_REFCLK0_N
VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
LOC = F20
| IOSTANDARD=LVCMOS18; # Bank
LOC = E20
| IOSTANDARD=LVCMOS18; # Bank
LOC = K17
| IOSTANDARD=LVCMOS18; # Bank
LOC = J17
| IOSTANDARD=LVCMOS18; # Bank
LOC = J20
| IOSTANDARD=LVCMOS18; # Bank
LOC = H20
| IOSTANDARD=LVCMOS18; # Bank
LOC = H18
| IOSTANDARD=LVCMOS18; # Bank
LOC = G17
| IOSTANDARD=LVCMOS18; # Bank
LOC = P18
| IOSTANDARD=LVCMOS18; # Bank
LOC = P17
| IOSTANDARD=LVCMOS18; # Bank
LOC = M17
| IOSTANDARD=LVCMOS18; # Bank
LOC = L17
| IOSTANDARD=LVCMOS18; # Bank
LOC = N19
| IOSTANDARD=LVCMOS18; # Bank
LOC = N18
| IOSTANDARD=LVCMOS18; # Bank
LOC = M19
| IOSTANDARD=LVCMOS18; # Bank
LOC = M18
| IOSTANDARD=LVCMOS18; # Bank
LOC = P20
| IOSTANDARD=LVCMOS18; # Bank
LOC = N20
| IOSTANDARD=LVCMOS18; # Bank
LOC = L20
| IOSTANDARD=LVCMOS18; # Bank
LOC = L19
| IOSTANDARD=LVCMOS18; # Bank
LOC = K20
| IOSTANDARD=LVCMOS18; # Bank
LOC = J16
| IOSTANDARD=LVCMOS18; # Bank
LOC = C16
| IOSTANDARD=LVCMOS18; # Bank
LOC = B16
| IOSTANDARD=LVCMOS18; # Bank
LOC = B14
| IOSTANDARD=LVCMOS18; # Bank
LOC = A14
| IOSTANDARD=LVCMOS18; # Bank
LOC = C15
| IOSTANDARD=LVCMOS18; # Bank
LOC = C14
| IOSTANDARD=LVCMOS18; # Bank
LOC = D13
| IOSTANDARD=LVCMOS18; # Bank
LOC = C13
| IOSTANDARD=LVCMOS18; # Bank
LOC = D16
| IOSTANDARD=LVCMOS18; # Bank
LOC = D15
| IOSTANDARD=LVCMOS18; # Bank
LOC = E12
| IOSTANDARD=LVDS;
LOC = D12
| IOSTANDARD=LVDS;
LOC = F16
| IOSTANDARD=LVCMOS18; # Bank
LOC = E15
| IOSTANDARD=LVCMOS18; # Bank
LOC = E14
| IOSTANDARD=LVCMOS18; # Bank
LOC = E13
| IOSTANDARD=LVCMOS18; # Bank
LOC = H16
| IOSTANDARD=LVCMOS18; # Bank
LOC = G16
| IOSTANDARD=LVCMOS18; # Bank
LOC = G12
| IOSTANDARD=LVCMOS18; # Bank
LOC = F12
| IOSTANDARD=LVCMOS18; # Bank
LOC = F15
| IOSTANDARD=LVCMOS18; # Bank
LOC = F14
| IOSTANDARD=LVCMOS18; # Bank
LOC = G14
| IOSTANDARD=LVCMOS18; # Bank
LOC = G13
| IOSTANDARD=LVCMOS18; # Bank
LOC = H15
| IOSTANDARD=LVCMOS18; # Bank
LOC = H14
| IOSTANDARD=LVCMOS18; # Bank
LOC = J13
| IOSTANDARD=LVCMOS18; # Bank
LOC = H13
| IOSTANDARD=LVCMOS18; # Bank
LOC = K12
| IOSTANDARD=LVCMOS18; # Bank
LOC = J12
| IOSTANDARD=LVCMOS18; # Bank
LOC = K15
| IOSTANDARD=LVCMOS18; # Bank
LOC = J15
| IOSTANDARD=LVCMOS18; # Bank
LOC = K14
| IOSTANDARD=LVCMOS18; # Bank
LOC = K13
| IOSTANDARD=LVCMOS18; # Bank
LOC = L16
| IOSTANDARD=LVCMOS18; # Bank
LOC = L15
| IOSTANDARD=LVCMOS18; # Bank
LOC = L12
| IOSTANDARD=LVDS;
LOC = L11
| IOSTANDARD=LVDS;
LOC = M14
| IOSTANDARD=LVCMOS18; # Bank
LOC = L14
| IOSTANDARD=LVCMOS18; # Bank
LOC = N16
| IOSTANDARD=LVCMOS18; # Bank
LOC = M16
| IOSTANDARD=LVCMOS18; # Bank
LOC = N13
| IOSTANDARD=LVCMOS18; # Bank
LOC = M13
| IOSTANDARD=LVCMOS18; # Bank
LOC = N15
| IOSTANDARD=LVCMOS18; # Bank
LOC = N14
| IOSTANDARD=LVCMOS18; # Bank
LOC = M12
| IOSTANDARD=LVCMOS18; # Bank
LOC = M11
| IOSTANDARD=LVCMOS18; # Bank
LOC = J11
| IOSTANDARD=LVCMOS18; # Bank
LOC = AW2
LOC = AW6
LOC = AW1
LOC = AW5
LOC = AY4
LOC = AY8
LOC = AY3
LOC = AW10
LOC = AY7
LOC = AW9
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# Bank
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# Bank
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# Bank
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# Bank
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; # Bank 111
; # Bank 111
; # Bank 111
; # Bank 111
; # Bank 111
; # Bank 111
; # Bank 111
; # Bank 111
; # Bank 111
; # Bank 111
VC7203 Board UCF Listing
57

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