Xilinx VC7203 User Manual page 25

Table 1-13: GTX Transceiver Pins (Cont'd)
Information for each GTX transceiver clock input is shown in
Table 1-14:
VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
U1 FPGA Pin Net Name
E4 118_RX0_P
E3 118_RX0_N
C4 118_TX1_P
C3 118_TX1_N
D6 118_RX1_P
D5 118_RX1_N
B2 118_TX2_P
B1 118_TX2_N
B6 118_RX2_P
B5 118_RX2_N
A4 118_TX3_P
A3 118_TX3_N
A8 118_RX3_P
A7 118_RX3_N
GTX Transceiver Reference Clock Inputs
U1 FPGA Pin Net Name
R8 115_REFCLK0_P
R7 115_REFCLK0_N
U8 115_REFCLK1_P
U7 115_REFCLK1_N
L8 116_REFCLK0_P
L7 116_REFCLK0_N
N8 116_REFCLK1_P
N7 116_REFCLK1_N
G8 117_REFCLK0_P
G7 117_REFCLK0_N
J8 117_REFCLK1_P
J7 117_REFCLK1_N
C8 118_REFCLK0_P
C7 118_REFCLK0_N
www.xilinx.com
Quad Connector
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
118 J86
Table
Quad Connector
115 J83
115 J83
115 J83
115 J83
116 J84
116 J84
116 J84
116 J84
117 J85
117 J85
117 J85
117 J85
118 J86
118 J86
Detailed Description
Trace Length
(mils)
3,048
3,049
2,629
2,628
2,597
2,597
2,787
2,789
2,681
2,680
3,044
3,044
3,515
3,515
1-14.
25