Xilinx VC7203 User Manual page 19

interface. The VC7203 board also supplies UTIL_5V0, UTIL_3V3, UTIL_2V5 and
VCCO_HR input power to the clock module interface.
Table 1-9: SuperClock-2 FPGA I/O Mapping
VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
U1 FPGA Pin Net Name
E12 CM_LVDS1_P
D12 CM_LVDS1_N
L12 CM_LVDS2_P
L11 CM_LVDS2_N
BA12 CM_LVDS3_P
BB12 CM_LVDS3_N
K19 CM_GCLK_P
J18 CM_GCLK_N
C19 CM_CTRL_0
B19 CM_CTRL_1
A16 CM_CTRL_2
A15 CM_CTRL_3
A20 CM_CTRL_4
A19 CM_CTRL_5
B17 CM_CTRL_6
A17 CM_CTRL_7
B21 CM_CTRL_8
A21 CM_CTRL_9
C18 CM_CTRL_10
B18 CM_CTRL_11
D20 CM_CTRL_12
C20 CM_CTRL_13
F17 CM_CTRL_14
E17 CM_CTRL_15
D21 CM_CTRL_16
C21 CM_CTRL_17
D18 CM_CTRL_18
D17 CM_CTRL_19
F20 CM_CTRL_20
E20 CM_CTRL_21
K17 CM_CTRL_22
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Detailed Description
J82 Pin
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