Xilinx VC7203 User Manual page 56

Appendix C: Master UCF Listing
NET FMC2_HA16_N
NET IO_25_VRP_36
NET IO_0_VRN_37
NET MGT_MOD_SPI_SCK
NET MGT_MOD_SPI_D
NET MGT_MOD_SPI_Q
NET GTX_MOD_SPI_CS
NET IO_L3P_T0_DQS_37
NET IO_L3N_T0_DQS_37
NET SA2_SDHOST_CMD
NET SA2_SDHOST_D0
NET SA2_SDHOST_D1
NET SA2_SDHOST_D3
NET SA2_SDHOST_D2
NET SA2_SDHOST_CLK
NET IO_L7P_T1_37
NET IO_L7N_T1_37
NET IO_L8P_T1_37
NET IO_L8N_T1_37
NET IO_L9P_T1_DQS_37
NET IO_L9N_T1_DQS_37
NET IO_L10P_T1_37
NET IO_L10N_T1_37
NET IO_L11P_T1_SRCC_37
NET IO_L11N_T1_SRCC_37
NET IO_L12P_T1_MRCC_37
NET IO_L12N_T1_MRCC_37
NET IO_L13P_T2_MRCC_37
NET IO_L13N_T2_MRCC_37
NET IO_L14P_T2_SRCC_37
NET IO_L14N_T2_SRCC_37
NET USB_GPIO_0
NET USB_GPIO_1
NET USB_GPIO_2
NET USB_GPIO_3
NET USB_TXD_0
NET USB_RXD_I
NET USB_RTS_0_B
NET USB_CTS_I_B
NET IO_L19P_T3_37
NET IO_L19N_T3_VREF_37
NET IO_L20P_T3_37
NET IO_L20N_T3_37
NET IO_L21P_T3_DQS_37
NET IO_L21N_T3_DQS_37
NET IO_L22P_T3_37
NET IO_L22N_T3_37
NET IO_L23P_T3_37
NET IO_L23N_T3_37
NET IO_L24P_T3_37
NET IO_L24N_T3_37
NET IO_25_VRP_37
NET IO_0_VRN_38
NET CM_CTRL_0
NET CM_CTRL_1
NET CM_CTRL_2
NET CM_CTRL_3
NET CM_CTRL_4
NET CM_CTRL_5
NET CM_CTRL_6
NET CM_CTRL_7
NET CM_CTRL_8
NET CM_CTRL_9
NET CM_CTRL_10
NET CM_CTRL_11
NET CM_CTRL_12
NET CM_CTRL_13
NET CM_CTRL_14
NET CM_CTRL_15
NET CM_CTRL_16
NET CM_CTRL_17
NET CM_CTRL_18
NET CM_CTRL_19
NET IO_L11P_T1_SRCC_38
NET IO_L11N_T1_SRCC_38
NET LVDS_OSC_P
NET LVDS_OSC_N
NET CLK_DIFF_1_P
NET CLK_DIFF_1_N
NET CM_GCLK_P
NET CM_GCLK_N
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LOC = L27 | IOSTANDARD=LVCMOS18; # Bank
LOC = M26 | IOSTANDARD=LVCMOS18; # Bank
LOC = F21 | IOSTANDARD=LVCMOS18; # Bank
LOC = A24 | IOSTANDARD=LVCMOS18; # Bank
LOC = A25 | IOSTANDARD=LVCMOS18; # Bank
LOC = B22 | IOSTANDARD=LVCMOS18; # Bank
LOC = A22 | IOSTANDARD=LVCMOS18; # Bank
LOC = A26 | IOSTANDARD=LVCMOS18; # Bank
LOC = A27 | IOSTANDARD=LVCMOS18; # Bank
LOC = C23 | IOSTANDARD=LVCMOS18; # Bank
LOC = B23 | IOSTANDARD=LVCMOS18; # Bank
LOC = B26 | IOSTANDARD=LVCMOS18; # Bank
LOC = B27 | IOSTANDARD=LVCMOS18; # Bank
LOC = C24 | IOSTANDARD=LVCMOS18; # Bank
LOC = B24 | IOSTANDARD=LVCMOS18; # Bank
LOC = E23 | IOSTANDARD=LVCMOS18; # Bank
LOC = E24 | IOSTANDARD=LVCMOS18; # Bank
LOC = F22 | IOSTANDARD=LVCMOS18; # Bank
LOC = E22 | IOSTANDARD=LVCMOS18; # Bank
LOC = F25 | IOSTANDARD=LVCMOS18; # Bank
LOC = E25 | IOSTANDARD=LVCMOS18; # Bank
LOC = D22 | IOSTANDARD=LVCMOS18; # Bank
LOC = D23 | IOSTANDARD=LVCMOS18; # Bank
LOC = D25 | IOSTANDARD=LVCMOS18; # Bank
LOC = D26 | IOSTANDARD=LVCMOS18; # Bank
LOC = C25 | IOSTANDARD=LVCMOS18; # Bank
LOC = C26 | IOSTANDARD=LVCMOS18; # Bank
LOC = D27 | IOSTANDARD=LVCMOS18; # Bank
LOC = D28 | IOSTANDARD=LVCMOS18; # Bank
LOC = C28 | IOSTANDARD=LVCMOS18; # Bank
LOC = C29 | IOSTANDARD=LVCMOS18; # Bank
LOC = B28 | IOSTANDARD=LVCMOS18; # Bank
LOC = B29 | IOSTANDARD=LVCMOS18; # Bank
LOC = A31 | IOSTANDARD=LVCMOS18; # Bank
LOC = A32 | IOSTANDARD=LVCMOS18; # Bank
LOC = A29 | IOSTANDARD=LVCMOS18; # Bank
LOC = A30 | IOSTANDARD=LVCMOS18; # Bank
LOC = C31 | IOSTANDARD=LVCMOS18; # Bank
LOC = B31 | IOSTANDARD=LVCMOS18; # Bank
LOC = E30 | IOSTANDARD=LVCMOS18; # Bank
LOC = D31 | IOSTANDARD=LVCMOS18; # Bank
LOC = D30 | IOSTANDARD=LVCMOS18; # Bank
LOC = C30 | IOSTANDARD=LVCMOS18; # Bank
LOC = E27 | IOSTANDARD=LVCMOS18; # Bank
LOC = E28 | IOSTANDARD=LVCMOS18; # Bank
LOC = F29 | IOSTANDARD=LVCMOS18; # Bank
LOC = E29 | IOSTANDARD=LVCMOS18; # Bank
LOC = F26 | IOSTANDARD=LVCMOS18; # Bank
LOC = F27 | IOSTANDARD=LVCMOS18; # Bank
LOC = F30 | IOSTANDARD=LVCMOS18; # Bank
LOC = F31 | IOSTANDARD=LVCMOS18; # Bank
LOC = F24 | IOSTANDARD=LVCMOS18; # Bank
LOC = K18 | IOSTANDARD=LVCMOS18; # Bank
LOC = C19 | IOSTANDARD=LVCMOS18; # Bank
LOC = B19 | IOSTANDARD=LVCMOS18; # Bank
LOC = A16 | IOSTANDARD=LVCMOS18; # Bank
LOC = A15 | IOSTANDARD=LVCMOS18; # Bank
LOC = A20 | IOSTANDARD=LVCMOS18; # Bank
LOC = A19 | IOSTANDARD=LVCMOS18; # Bank
LOC = B17 | IOSTANDARD=LVCMOS18; # Bank
LOC = A17 | IOSTANDARD=LVCMOS18; # Bank
LOC = B21 | IOSTANDARD=LVCMOS18; # Bank
LOC = A21 | IOSTANDARD=LVCMOS18; # Bank
LOC = C18 | IOSTANDARD=LVCMOS18; # Bank
LOC = B18 | IOSTANDARD=LVCMOS18; # Bank
LOC = D20 | IOSTANDARD=LVCMOS18; # Bank
LOC = C20 | IOSTANDARD=LVCMOS18; # Bank
LOC = F17 | IOSTANDARD=LVCMOS18; # Bank
LOC = E17 | IOSTANDARD=LVCMOS18; # Bank
LOC = D21 | IOSTANDARD=LVCMOS18; # Bank
LOC = C21 | IOSTANDARD=LVCMOS18; # Bank
LOC = D18 | IOSTANDARD=LVCMOS18; # Bank
LOC = D17 | IOSTANDARD=LVCMOS18; # Bank
LOC = G19 | IOSTANDARD=LVCMOS18; # Bank
LOC = F19 | IOSTANDARD=LVCMOS18; # Bank
LOC = E19 | IOSTANDARD=LVDS;
LOC = E18 | IOSTANDARD=LVDS;
LOC = H19 | IOSTANDARD=LVCMOS18; # Bank
LOC = G18 | IOSTANDARD=LVCMOS18; # Bank
LOC = K19 | IOSTANDARD=LVCMOS18; # Bank
LOC = J18 | IOSTANDARD=LVCMOS18; # Bank
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# Bank 38
# Bank 38
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VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012