Xilinx VC7203 User Manual page 23

X-Ref Target - Figure 1-11
Information for each GTX transceiver pin is shown in
Table 1-13: GTX Transceiver Pins
VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012
A
GTX Connector Pad
Figure 1-11: A – GTX Connector Pad. B – GTX Connector Pinout
U1 FPGA Pin Net Name
Y2 115_TX0_P
Y1 115_TX0_N
AA4 115_RX0_P
AA3 115_RX0_N
V2 115_TX1_P
V1 115_TX1_N
Y6 115_RX1_P
Y5 115_RX1_N
U4 115_TX2_P
U3 115_TX2_N
W4 115_RX2_P
W3 115_RX2_N
T2 115_TX3_P
T1 115_TX3_N
V6 115_RX3_P
V5 115_RX3_N
P2 116_TX0_P
P1 116_TX0_N
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B
GTX
N
P N
N
P N
N
P N
N
P N
N
P N
GTX Connector Pinout
UG957_c1_11_100712
Table 1-13.
Quad Connector
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
115 J83
116 J84
116 J84
Detailed Description
P
P
P
P
P
Trace Length
(mils)
2,805
2,806
2,898
2,898
2,525
2,523
2,489
2,489
2,549
2,549
2,308
2,309
2,840
2,840
2,933
2,933
2,677
2,677
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