Xilinx VC7203 User Manual page 48

Appendix C: Master UCF Listing
NET IO_0_VRN_13
NET IO_L1P_T0_13
NET IO_L1N_T0_13
NET IO_L2P_T0_13
NET IO_L2N_T0_13
NET IO_L3P_T0_DQS_13
NET IO_L3N_T0_DQS_13
NET IO_L4P_T0_13
NET IO_L4N_T0_13
NET IO_L5P_T0_13
NET IO_L5N_T0_13
NET IO_L6P_T0_13
NET IO_L6N_T0_VREF_13
NET IO_L7P_T1_13
NET IO_L7N_T1_13
NET IO_L8P_T1_13
NET IO_L8N_T1_13
NET IO_L9P_T1_DQS_13
NET IO_L9N_T1_DQS_13
NET IO_L10P_T1_13
NET IO_L10N_T1_13
NET IO_L11P_T1_SRCC_13
NET IO_L11N_T1_SRCC_13
NET IO_L12P_T1_MRCC_13
NET IO_L12N_T1_MRCC_13
NET IO_L13P_T2_MRCC_13
NET IO_L13N_T2_MRCC_13
NET IO_L14P_T2_SRCC_13
NET IO_L14N_T2_SRCC_13
NET IO_L15P_T2_DQS_13
NET IO_L15N_T2_DQS_13
NET IO_L16P_T2_13
NET IO_L16N_T2_13
NET IO_L17P_T2_13
NET IO_L17N_T2_13
NET IO_L18P_T2_13
NET IO_L18N_T2_13
NET IO_L19P_T3_13
NET IO_L19N_T3_VREF_13
NET IO_L20P_T3_13
NET IO_L20N_T3_13
NET IO_L21P_T3_DQS_13
NET IO_L21N_T3_DQS_13
NET IO_L22P_T3_13
NET IO_L22N_T3_13
NET IO_L23P_T3_13
NET IO_L23N_T3_13
NET IO_L24P_T3_13
NET IO_L24N_T3_13
NET IO_25_VRP_13
NET IO_0_VRN_14
NET FMC1_LA19_P
NET FMC1_LA19_N
NET FMC1_LA20_P
NET FMC1_LA20_N
NET FMC1_LA21_P
NET FMC1_LA21_N
NET FMC1_LA22_P
NET FMC1_LA22_N
NET FMC1_LA23_P
NET FMC1_LA23_N
NET FMC1_LA24_P
NET FMC1_LA24_N
NET FMC1_LA25_P
NET FMC1_LA25_N
NET FMC1_LA26_P
NET FMC1_LA26_N
NET FMC1_LA27_P
NET FMC1_LA27_N
NET FMC1_LA28_P
NET FMC1_LA28_N
NET FMC1_LA18_CC_P
NET FMC1_LA18_CC_N
NET FMC1_LA17_CC_P
NET FMC1_LA17_CC_N
NET FMC1_CLK0_M2C_P
NET FMC1_CLK0_M2C_N
NET FMC1_CLK1_M2C_P
NET FMC1_CLK1_M2C_N
NET FMC1_LA29_P
NET FMC1_LA29_N
48
LOC = AR35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY34 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW36 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA34 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB34 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA36 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB36 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB32 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY33 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA31 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY30 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA30 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP30 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM37 | IOSTANDARD=LVCMOS18; # Bank
LOC = AG33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AH34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ35 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK33 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL31 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL32 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM34 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN34 | IOSTANDARD=LVCMOS18; # Bank
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VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012