Xilinx VC7203 User Manual page 52

Appendix C: Master UCF Listing
NET CLK_DIFF_2_N
NET IO_L13P_T2_MRCC_19
NET IO_L13N_T2_MRCC_19
NET DUT_I2C_SCL
NET DUT_I2C_SDA
NET IO_L15P_T2_DQS_19
NET IO_L15N_T2_DQS_19
NET IO_L16P_T2_19
NET IO_L16N_T2_19
NET IO_L17P_T2_19
NET IO_L17N_T2_19
NET IO_L18P_T2_19
NET IO_L18N_T2_19
NET USER_PB1
NET USER_PB2
NET APP_LED1
NET APP_LED2
NET APP_LED3
NET APP_LED4
NET APP_LED5
NET APP_LED6
NET APP_LED7
NET APP_LED8
NET IO_L24P_T3_19
NET IO_L24N_T3_19
NET IO_25_VRP_19
NET IO_0_VRN_31
NET FMC3_LA02_P
NET FMC3_LA02_N
NET FMC3_LA03_P
NET FMC3_LA03_N
NET FMC3_LA04_P
NET FMC3_LA04_N
NET FMC3_LA05_P
NET FMC3_LA05_N
NET FMC3_LA06_P
NET FMC3_LA06_N
NET FMC3_LA07_P
NET FMC3_LA07_N
NET FMC3_LA08_P
NET FMC3_LA08_N
NET FMC3_LA09_P
NET FMC3_LA09_N
NET FMC3_LA10_P
NET FMC3_LA10_N
NET FMC3_LA11_P
NET FMC3_LA11_N
NET FMC3_LA01_CC_P
NET FMC3_LA01_CC_N
NET FMC3_LA00_CC_P
NET FMC3_LA00_CC_N
NET FMC3_HA00_CC_P
NET FMC3_HA00_CC_N
NET FMC3_HA01_CC_P
NET FMC3_HA01_CC_N
NET FMC3_LA12_P
NET FMC3_LA12_N
NET FMC3_LA13_P
NET FMC3_LA13_N
NET FMC3_LA14_P
NET FMC3_LA14_N
NET FMC3_LA15_P
NET FMC3_LA15_N
NET FMC3_LA16_P
NET FMC3_LA16_N
NET FMC3_HA02_P
NET FMC3_HA02_N
NET FMC3_HA03_P
NET FMC3_HA03_N
NET FMC3_HA04_P
NET FMC3_HA04_N
NET FMC3_HA05_P
NET FMC3_HA05_N
NET CM_LVDS3_P
NET CM_LVDS3_N
NET IO_25_VRP_31
NET FMC3_PRSNT_M2C_L
NET FMC3_LA19_P
NET FMC3_LA19_N
NET FMC3_LA20_P
NET FMC3_LA20_N
52
LOC = K40 | IOSTANDARD=LVCMOS18; # Bank
LOC = L39 | IOSTANDARD=LVCMOS18; # Bank
LOC = L40 | IOSTANDARD=LVCMOS18; # Bank
LOC = M41 | IOSTANDARD=LVCMOS18; # Bank
LOC = L41 | IOSTANDARD=LVCMOS18; # Bank
LOC = K42 | IOSTANDARD=LVCMOS18; # Bank
LOC = J42 | IOSTANDARD=LVCMOS18; # Bank
LOC = M42 | IOSTANDARD=LVCMOS18; # Bank
LOC = L42 | IOSTANDARD=LVCMOS18; # Bank
LOC = K37 | IOSTANDARD=LVCMOS18; # Bank
LOC = K38 | IOSTANDARD=LVCMOS18; # Bank
LOC = M36 | IOSTANDARD=LVCMOS18; # Bank
LOC = L37 | IOSTANDARD=LVCMOS18; # Bank
LOC = P41 | IOSTANDARD=LVCMOS18; # Bank
LOC = N41 | IOSTANDARD=LVCMOS18; # Bank
LOC = M37 | IOSTANDARD=LVCMOS18; # Bank
LOC = M38 | IOSTANDARD=LVCMOS18; # Bank
LOC = R42 | IOSTANDARD=LVCMOS18; # Bank
LOC = P42 | IOSTANDARD=LVCMOS18; # Bank
LOC = N38 | IOSTANDARD=LVCMOS18; # Bank
LOC = M39 | IOSTANDARD=LVCMOS18; # Bank
LOC = R40 | IOSTANDARD=LVCMOS18; # Bank
LOC = P40 | IOSTANDARD=LVCMOS18; # Bank
LOC = N39 | IOSTANDARD=LVCMOS18; # Bank
LOC = N40 | IOSTANDARD=LVCMOS18; # Bank
LOC = N36 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ16 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AJ12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL16 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM11 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AN11 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP11 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW13 | IOSTANDARD=LVCMOS18; # Bank
LOC = AP12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AT12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AU12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AV14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AW12 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY12 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA15 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY14 | IOSTANDARD=LVCMOS18; # Bank
LOC = AY13 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB14 | IOSTANDARD=LVCMOS18; # Bank
LOC = BB13 | IOSTANDARD=LVCMOS18; # Bank
LOC = BA12 | IOSTANDARD=LVDS;
LOC = BB12 | IOSTANDARD=LVDS;
LOC = AP15 | IOSTANDARD=LVCMOS18; # Bank
LOC = AR20 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL19 | IOSTANDARD=LVCMOS18; # Bank
LOC = AM19 | IOSTANDARD=LVCMOS18; # Bank
LOC = AK17 | IOSTANDARD=LVCMOS18; # Bank
LOC = AL17 | IOSTANDARD=LVCMOS18; # Bank
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# Bank 31
# Bank 31
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VC7203 GTX Transceiver Characterization Board
UG957 (v1.0) October 10, 2012