Writeback; Writeback Arbitration - Freescale Semiconductor PowerPC MPC823 Reference Manual

8.2.2 Writeback

8.2.2.1 WRITEBACK ARBITRATION

mulli r12,r4,3
sub
r3,r15,3
addic r4,r12,1
GCLK1
MULLI
FETCH
DECODE
READ + EXECUTE
WRITEBACK
Figure 8-2. Example of a Writeback Arbitration
The addic instruction is dependent on the mulli result. Since the single-cycle instruction
sub has priority on the writeback bus over the mulli and the mulli writeback is delayed one
clock and causes a bubble in the execute stream.
mulli r12,r4,3
sub
r3,r15,3
addic r4,r3,1
GCLK1
MULLI
FETCH
DECODE
READ + EXECUTE
WRITEBACK
Figure 8-3. Another Example of a Writeback Arbitration
Freescale Semiconductor, Inc.
SUB ADDIC
MULLI SUB
MULLI SUB, MULLI
SUB ADDIC
MULLI SUB
MULLI SUB, MULLI
MPC823 REFERENCE MANUAL
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Instruction Execution Timing
ADDIC
BUBBLE ADDIC
SUB
MULLI
ADDIC
ADDIC
SUB
ADD MULLI
ADD
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