Mmu Data Effective Page Number Register - Freescale Semiconductor PowerPC MPC823 Reference Manual

Memory Management Unit
11.6.1.5 MMU DATA EFFECTIVE PAGE NUMBER REGISTER. The MMU data effective
page number (MD_EPN) register contains the effective address to be loaded into a TLB
entry.
MD_EPN
BIT 0 1 2
FIELD
RESET
R/W
ADDR
BIT 16 17 18
FIELD
RESET
R/W
ADDR
NOTE: — = Undefined.
EPN—Effective Page Number for Entry
The default value is the effective address of the last data TLB miss.
EV—TLB Entry Valid
This bit is set to 1 on a data TLB miss.
0 = The data TLB entry is invalid.
1 = The data TLB entry is valid.
Bits 23–27—Reserved
These bits are reserved and must be set to 0. Ignores on write and returns a 0 on read.
ASID—Address Space ID
This field is the address space IDs of the TLB entry to be compared with the CASID field of
the M_CASID register.
Freescale Semiconductor, Inc.
3 4 5 6
19 20 21 22
EPN EV
— —
R/W R/W
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7 8 9 10 11
EPN
—
R/W
SPR 795
23 24 25 26 27
RESERVED
0
R/W
SPR 795
12 13 14 15
28 29 30 31
ASID
—
R/W
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