Digital Timing Diagrams - Analog Devices ADAU1961 Manual

ADAU1961

DIGITAL TIMING DIAGRAMS

BCLK
LRCLK
DAC_SDATA
LEFT-JUSTIFIED
MODE
DAC_SDATA
2
I S MODE
DAC_SDATA
RIGHT-JUSTIFIED
MODE
BCLK
LRCLK
ADC_SDATA
LEFT-JUSTIFIED
MODE
ADC_SDATA
2
I S MODE
ADC_SDATA
RIGHT-JUSTIFIED
MODE
Downloaded from Elcodis.com electronic components distributor
t
BIH
t
BIL
t
LIS
t
SIS
MSB
MSB – 1
t
SIH
t
SIS
MSB
t
SIH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
t
BIH
t
BIL
t
SODM
MSB MSB – 1
t
SODM
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
14-BIT CLOCKS
(18-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Serial Output Port Timing
t
SIS
MSB
t
SIH
Figure 2. Serial Input Port Timing
t
SODM
MSB
Rev. 0 | Page 10 of 76
t
LIH
t
SIS
LSB
t
SIH
LSB