Timing Diagrams - Analog Devices ADAV4622 Manual

ADAV4622

TIMING DIAGRAMS

MCLKI
RESET
t f
= 1/
MP MCLKI
Figure 2. Master Clock and Reset Timing
DVDD
GND
t
CH
Figure 3. Master Clock Output Timing
LRCLK1 t
SLS
BCLK1
SDINx
t
SDS
SDO0
Figure 4. Serial Port Slave Mode Timing
t
MLD
LRCLK1
BCLK1
SDINx
t
MDS
SDO0
Figure 5. Serial Port Master Mode Timing
TO OUTPUT
PIN
50pF
Figure 6. Load Circuit for Digital Output Timing Specifications
t
RESET
t
CL
t
CK
t
SLH
t
SDH
t
SDD
t
MDH
t
MDD
100µA I
OL
ODVDD
100µA I
OH
Rev. B | Page 10 of 28
t
JIT