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CrossLink-NX Evaluation Board
User Guide
5
J7
1
2
1
2
V1P8_LDO
Header_2x1
FB1
R42
MPZ1005S121CT000
0.1
PLL filter with DCR<=0.1 ohm
1%
C43
0603
10uF
DC must be <<5% drop across
D
anti-resonance resistor under
Ref_return_pll
worst case
Place PLL series resistor,
R45
two caps and r_ext right
1.15K
underneath the chip on the
R_ext
reverse side of the board
R_ext is chosen for 100 ohm Diff
J9
1
2
1
2
V1P8_LDO
Header_2x1
TP_V1P8_VCCAUXSD
FB3
R53
MPZ1005S121CT000
0.1
1%
C51
0603
10uF
C
Ref_return_pll
VCCIO2
C58
C59
C60
10uF
0.1uF
0.1uF
VCCIO2
U3C
U19
N14
SWITCH0
B
VCCIO2
PR24A
N17
M14
SWITCH1
VCCIO2
PR24B
M16
SWITCH2
PR26A
M15
SWITCH3
PR26B
N15
SWITCH4
PR27A
N16
SWITCH5
PR27B
M17
SWITCH6
PR30A/PCLKT2_0
M18
SWITCH7
PR30B
M19
PR32A/PCLKT2_1
M20
PR32B
N19
PR34A/PCLKT2_2
N20
PR34B
P19
PR36A
P20
PR36B
P17
PR38A
P18
PR38B
Bank2
R17
LED8
PR40A
R18
LED9
PR40B
U20
LED10
PR42A
T20
LED11
PR42B
W20
LED12
PR44A
3.3v
V20
LED13
PR44B
T18
short_stub_trace
PR46A
U18
PR46B
V18
6_inch_long_trace
A
PR47A
V19
PR47B
W19
PR49A
Y19
PR49B
R19
NC27
R20
NC26
P15
NC29
P16
NC28
LIFCL-40-BG400
5
© 2019-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
4
TP_V1P8_VCCPLLSD
J8
1
1
2
C44
Header_2x1
V1P0_LDO
0.1uF
FB2
R44
MPZ1005S121CT000
0.1
1%
0603
V3P3
L10
2
1
600ohm 500mA
C48
C49
0.1uF
C52
0.1uF
VCCIO2
V3P3
L11
2
1
600ohm 500mA
8
9
4_7K
RN1H
EXB2HV472JV
1
4_7K
16
RN1A
EXB2HV472JV
C56
C57
5
4_7K
12
RN1E
0.1uF
EXB2HV472JV
2
4_7K
15
RN1B
EXB2HV472JV
7
10
4_7K
RN1G
EXB2HV472JV
6
4_7K
11
RN1F
J13
EXB2HV472JV
3
4_7K
14
RN1C
CON3
EXB2HV472JV
4
4_7K
13
RN1D
DIP SWITCH
EXB2HV472JV
SW1
SWITCH0
FMC_SDA
{10}
SWITCH1
FMC_SCL
{10}
SWITCH2
PS_POR_B
{10}
SWITCH3
FMC_PRSNT
{10}
SWITCH4
FMC_TCK
{10}
SWITCH5
FMC_TDI
{10}
SWITCH6
FMC_TDO
{10}
SWITCH7
FMC_TMS
{10}
LED8
{7}
SMD SW DIP-8
LED9
{7}
Part Number = 219-8MST
LED10
{7}
TP3
LED11
{7}
Minimize length as short as possible
LED12
{7}
LED13
{7}
short_stub_trace. TP close to FPGA
10_inch_long_trace
Two 50 ohm Lookbacks Traces: 6 inches and 10 inches
Place TPs close to FPGA
4
Figure A.6. SERDES SMAs/Switches/FMC Control
3
Serdes Bank
U3L
C13
VCCPLLSD0
B11
VCCAUXSD
SD0_REFRET
2
B15
VCCSD0_1
B13
VCCSD0_2
TP_V1P0_VCCSD
SD0_REFCLKP
SD0_REFCLKN
LIFCL-40-BG400
C45
C46
C47
10uF
0.1uF
0.1uF
R50
10K
U4
AK5DAF1-125.0000T2
1
4
125MHz
R54
0
OE
OP
5
125MHz_N
R56
0
ON
2
NC
OSCP
OSCN
R62
10K
U5
AK5DAF1-200.0000T2
1
4
200MHz
R65
0
DNI
OE
OP
5
200MHz_N
R66
0
DNI
ON
2
NC
DNI
1-2 = 125 Mhz (Default)
2-3 = 200 Mhz
Switch Signal Map
U3C Pin
Signal
N14
SWITCH0
M14
SWITCH1
TP4
M16
SWITCH2
TP5
M15
SWITCH3
N15
SWITCH4
N16
SWITCH5
M17
SWITCH6
M18
SWITCH7
3
2
C14
R_ext
SD0_REXT
A16
RXDPF
R41
DNI
100 ohm
SD0_RXDP
A15
RXDNF
SD0_RXDN
Ref_return_pll
B14
A13
TXDPF
SD0_TXDP
A12
TXDNF
SD0_TXDN
C12
REFCLKP
R43
DNI
100 ohm
C11
REFCLKN
R46
0
OSCP
REFCLKP
R47
DNI
0
REFCLKP_SMA
R48
DNI
0
R49
0
OSCN
REFCLKN
R51
DNI
0
REFCLKN_SMA
R52
DNI
0
C50
RXDPF
RXDP
R55
0
RXDP_SMA
0.1uF
R57
DNI
0
C53
RXDNF
RXDN
R58
0
RXDN_SMA
0.1uF
R59
DNI
0
C54
TXDPF
TXDP
R60
0
TXDP_SMA
0.1uF
R61
DNI
0
C55
TXDNF
TXDN
R63
0
TXDN_SMA
0.1uF
R64
DNI
0
J10
J11
REFCLKP_SMA
RXDP_SMA
2
1
2
1
3
3
4
4
5
5
SMA
SMA
DNI
DNI
J14
J15
2
1
REFCLKN_SMA
2
1
RXDN_SMA
3
3
4
4
5
5
SMA
SMA
DNI
DNI
Route SMA pairs as 100 ohm differential
SWITCH
1
2
3
4
5
Lattice Semiconductor Applications
Lattice Semiconductor Applications
Lattice Semiconductor Applications
http://www.latticesemi.com/Support
http://www.latticesemi.com/Support
http://www.latticesemi.com/Support
6
Title
Title
Title
7
Serdes SMAs/Switches/FMC Control
Serdes SMAs/Switches/FMC Control
Serdes SMAs/Switches/FMC Control
8
Size
Size
Size
Project
Project
Project
B
B
B
CrossLink-NX Evaluation Board
CrossLink-NX Evaluation Board
CrossLink-NX Evaluation Board
Date:
Date:
Date:
Friday, Nov 22, 2019
Friday, Nov 22, 2019
Friday, Nov 22, 2019
2
1
Use little to no stub
between selection
D
resistors
REFCLKP_FMC
{10}
REFCLKN_FMC
{10}
RXDP_FMC
{10}
C
RXDN_FMC
{10}
TXDP_FMC
{10}
TXDN_FMC
{10}
J12
TXDP_SMA
2
1
3
4
5
SMA
DNI
B
J16
2
1
TXDN_SMA
3
4
5
SMA
DNI
A
Schematic Rev
Schematic Rev
Schematic Rev
B-1
B-1
B-1
Board Rev
Board Rev
Board Rev
B
B
B
Sheet
Sheet
Sheet
6
6
6
of
of
of
14
14
14
1
FPGA-EB-02028-1.4
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