Serdes Channels - Lattice Semiconductor LatticeSC PCI Express x1 User Manual

Lattice Semiconductor

SERDES Channels

SMA Connections
(see Appendix A, Figure 5)
DC coupled top-mounted SMA connectors connect to the two SERDES TX and RX channels. These pins are
directly coupled to the designated SMA connector creating a path for both input and output differential data.
Table 9. SERDES Connectors (see Appendix A, Figure 8)
SMA
J13
J15
J9
J11
SERDES SFP Transceiver Interface
(see Appendix A, Figure 8)
A small form-factor pluggable (SFP) transceiver cage is included for evaluation of SFP specific protocols. The PCB
includes the appropriate power and high-speed circuitry needed for the SFP standard transceiver.
Table 10. SFP Connections to SERDES Pins (see Appendix A, Figure 5)
SFP RX
RD+
RD-
Table 11. SFP Control and Status Connections to FPGA
SERDES SATA Channels
(see Appendix A, Figure 8)
AC-coupled connections are included to attach SATA type cables to SERDES channels for board-to-board or loop-
back purposes. The connectors are configured using the 7-pin SATA specifications.
900-Ball
Channel Name
A_HDINP1_LEFT
A_HDINN1_LEFT
A_HDINP2_LEFT
A_HDINN2_LEFT
900-Ball
Channel Name fpBGA
A_HDINP0_RIGHT
A_HDINN0_RIGHT
900-Ball
SFP Pin
TxFault
TxDis
LOS
RateSel
fpBGA SMA
B6 J10
B5 J12
B7 J14
B8 J16
SFP TX
B28 TD+ A_HDOUTP0_RIGHT
B27 TD- A_HDOUTN0_RIGHT
fpBGA SFP Pin
A15 ModeDef0
C13 ModeDef1
G15 ModeDef3
F15
10
LatticeSC PCI Express x1
Evaluation Board User's Guide
900-Ball
Channel Name
A_HDOUTP1_LEFT
A_HDOUTN1_LEFT
A_HDOUTP2_LEFT
A_HDOUTN2_LEFT
900-Ball
Channel Name
900-Ball
fpBGA
E15
D15
C14
fpBGA
A6
A5
A7
A8
fpBGA
A28
A27