Contents
Acronyms in This Document ................................................................................................................................................. 5
1.
Introduction .................................................................................................................................................................. 6
1.1.
CrossLink-NX Evaluation Board ........................................................................................................................... 6
1.2.
Features .............................................................................................................................................................. 6
1.3.
CrossLink-NX Device .......................................................................................................................................... 11
1.4.
Applying Power to the Board ............................................................................................................................ 11
2.
Jumpers and Test Connection .................................................................................................................................... 12
3.
Power Scheme ............................................................................................................................................................ 14
2
4.
C .................................................................................................................................................. 15
4.1.
JTAG Download Interface .................................................................................................................................. 15
4.2.
4.3.
4.4.
4.5.
Other JTAG Configuration Pins .......................................................................................................................... 17
5.
CrossLink-NX Clock Sources ........................................................................................................................................ 18
2
6.
C, UART, and SPI ............................................................................................................................. 19
2
6.1.
C ...................................................................................................................................................................... 19
6.2.
UART Topology .................................................................................................................................................. 19
6.3.
SPI Topology ...................................................................................................................................................... 20
SPI Configuration .......................................................................................................................................... 20
7.
LEDs and Switches ...................................................................................................................................................... 21
7.1.
DIP Switch ......................................................................................................................................................... 21
7.2.
General Purpose Push Buttons ......................................................................................................................... 21
7.3.
General Purpose LEDs ....................................................................................................................................... 22
7.4.
Indicator LEDs .................................................................................................................................................... 22
8.
8.1.
FMC LPC Connector ........................................................................................................................................... 23
8.2.
8.3.
Raspberry Pi Board GPIO Header ...................................................................................................................... 25
8.4.
Camera Connector ............................................................................................................................................ 26
8.5.
D-PHY1 Header .................................................................................................................................................. 27
8.6.
PMOD Header ................................................................................................................................................... 28
8.7.
JTAG Header ...................................................................................................................................................... 28
8.8.
Parallel Configuration Header ........................................................................................................................... 29
8.9.
ADC Test Header ............................................................................................................................................... 29
9.
Software Requirements .............................................................................................................................................. 30
10.
Storage and Handling ............................................................................................................................................. 30
11.
Ordering Information .............................................................................................................................................. 30
References .......................................................................................................................................................................... 56
Lattice Semiconductor Documents ................................................................................................................................. 56
Technical Support Assistance .............................................................................................................................................. 57
Revision History .................................................................................................................................................................. 58
© 2019-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.4
CrossLink-NX Evaluation Board
User Guide
3