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8. Headers/Connectors and LIFCL-40 Device Ball Mapping
This section describes the CrossLink-NX Evaluation Board headers/connectors and ball mapping.
8.1. FMC LPC Connector
Table 8.1. FMC LPC Header Pin Connections
U9 Pin Name
Signal Name
C1
C2
TXDP_FMC
C3
TXDN_FMC
C4
C5
C6
RXDP_FMC
C7
RXDN_FMC
C8
C9
C10
FMC_LA06_P
C11
FMC_LA06_N
C12
C13
C14
FMC_LA10_P
C15
FMC_LA10_N
C16
C17
C18
FMC_LA14_P
C19
FMC_LA14_N
C20
C21
C22
FMC_LA18_CC_P
C23
FMC_LA18_CC_N
C24
C25
C26
FMC_LA27_P
C27
FMC_LA27_N
C28
C29
C30
FMC_SCL
C31
FMC_SDA
C32
C33
C34
C35
C36
C37
C38
C39
C40
G1
© 2019-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.4
LIFCL-40 Ball
GND
—
—
—
GND
—
GND
—
—
—
GND
—
GND
—
W9
Y9
GND
—
GND
—
W10
Y10
GND
—
GND
—
W11
Y11
GND
—
GND
—
R8
T8
GND
—
GND
—
Y13
Y14
GND
—
GND
—
—
—
GND
—
GND
—
GND
—
12V
—
GND
—
12V
—
GND
—
V3P3
—
GND
—
GND
—
U9 Pin Name
Signal Name
D1
PS_POR_B
D2
GND
D3
GND
D4
REFCLKP_FMC
D5
REFCLKN_FMC
D6
GND
D7
GND
D8
FMC_LA01_CC_P
D9
FMC_LA01_CC_N
D10
GND
D11
FMC_LA05_P
D12
FMC_LA05_N
D13
GND
D14
FMC_LA09_P
D15
FMC_LA09_N
D16
GND
D17
FMC_LA13_P
D18
FMC_LA13_N
D19
GND
D20
FMC_LA17_P
D21
FMC_LA17_N
D22
GND
D23
FMC_LA23_P
D24
FMC_LA23_N
D25
GND
D26
FMC_LA26_P
D27
FMC_LA26_N
D28
GND
D29
FMC_TCK
D30
FMC_TDI
D31
FMC_TDO
D32
V3P3
D33
FMC_TMS
D34
NO Connect
D35
GND
D36
V3P3
D37
GND
D38
V3P3
D39
GND
D40
V3P3
H1
FMC_VREF
CrossLink-NX Evaluation Board
User Guide
LIFCL-40 Ball
—
—
—
—
—
—
—
W13
V12
—
R5
R6
—
V6
U7
—
R9
P9
—
U10
V10
—
P11
R11
—
T13
T14
—
—
—
—
—
—
—
—
—
—
—
—
—
T6 Y18
23
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