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Lattice Semiconductor LatticeXP2 User Manual

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LatticeXP2 Standard Evaluation Board
User's Guide
May 2008
Revision: EB29_01.4

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Summary of Contents for Lattice Semiconductor LatticeXP2

  • Page 1 LatticeXP2 Standard Evaluation Board User’s Guide May 2008 Revision: EB29_01.4...
  • Page 2 Boot technologies. The LatticeXP2 devices include LUT-based logic, distributed and embedded memory, Phase Locked Loops (PLLs), pre-engineered source synchronous I/O and enhanced sysDSP™ blocks. For a full description of the LatticeXP2 FPGA, see the Lattice website for data sheets, technical notes, technology summaries and more: www.latticesemi.com.

  • Page 3: Additional Resources

    Other features on the board are useful for evaluation of the LatticeXP2 FPGA or development of more complex solutions. The A/D, D/A, and digital potentiometer are helpful for mixed signal applications. SMA connections can be used for the evaluation of high-speed differential signals, and protocols.

  • Page 4: Power Supply

    The Power Manager uses this supply rail to boot and run a power up sequence. While the LatticeXP2 does not require any specific order for the voltage rails to be applied, the Power Manager can be used to try a wide variety of sequence options.
  • Page 5 VAdj from U4 (1.1V-2.5V). Use R10 to adjust the output. 3.3V Programmability There are three programmable devices on the board. Of primary interest for the FPGA user is the LatticeXP2. How- ever, the ispPAC-POWR607 Power Manager, and the MachXO™2280 are also important to the overall operation of the board.
  • Page 6 LatticeXP2 FPGA. The serial output from the LatticeXP2 is routed to J29. A jumper on J29 directs the serial output of the LatticeXP2 back to the USB cable/J34. This is the factory default configuration and is expected to be the pri- mary JTAG mode for most users.
  • Page 7 The LatticeXP2 has configuration pins that define how the device will find a non-volatile bitstream to configure itself. In most cases the configuration pins will be set to have the LatticeXP2 act as a master device and actively read data from its internal Flash or from the attached SPI PROM.

  • Page 8: Led Displays

    Global Output Enable The LatticeXP2 has a global output enable control. The GOE is routed to J15, and the factory default setting on J15 is to enable the LatticeXP2 outputs. The jumper on J15 can be moved from the default setting (open) to disable (tri- state) all of the LatticeXP2 I/Os.

  • Page 9: Oscillator And Clock Inputs

    FPGA logic. Reference frequencies can be applied to other LatticeXP2 clock inputs as well. The LatticeXP2 board provides a low-voltage (3.3V) DIP oscillator. The oscillator is installed in a 14-pin DIP socket. The socket permits the use of either a half-size or full-size DIP oscillator.
  • Page 10 Y (N) Power Supplies and Supply Control The LatticeXP2 Standard Evaluation Board operates from a 5V DC input voltage. The input voltage is supplied via J9, a coaxial DC input jack. The following components operate using the 5V input: • ispPAC-POWR607 Power Manager...
  • Page 11 J12 is used to configure the I/O voltage used by Bank 6. U6 is a fixed 3.3V supply. It provides 3.3V to all of the ICs on the board, as well as the LatticeXP2’s VCCAUX and VCCIO banks (except Bank 6). The 3.3V provided to VCCAUX and VCCIO pass through R17, a 10 mOhm current sense resistor.

  • Page 12: Lcd Connector

    J16-8 J16-7 The LatticeXP2 FPGA is connected to the RS232 DB9 connector using a Max 3232 buffer chip. This buffer permits the LatticeXP2 3.3V I/O pins to be interfaced to the 12V RS232 signaling standard. The LatticeXP2 I/O pins that connect to the RS232 buffer listed in Table 13.

  • Page 13: Compact Flash Connector

    CF22 CF45 Mixed Signal Support The LatticeXP2 Standard Evaluation Board also provides access to some mixed signal interface chips. There are four primary components dedicated to performing mixed signal functions on the evaluation board. These compo- nents are: • 12-bit Analog to Digital Converter •...
  • Page 14 The digital I/O side of the device connects directly to the LatticeXP2 FPGA. Twelve of the I/O are the data-bus pins, and seven are used to access the internal registers.

  • Page 15: Ordering Information

    SRAM Function LatticeXP2 I/O AA17 AB10 AB17 AA10 AB12 AA13 AA14 AA15 AA16 AB16 AB15 AA22 AB14 AB13 AA21 AA20 AB20 AB11 AB19 AB18 Ordering Information China RoHS Environment-Friendly Description Ordering Part Number Use Period (EFUP) LatticeXP2 Standard Evaluation Board LFXP2-17E-L-EV...

  • Page 16: Technical Support Assistance

    01.4 Corrected LatticeXP2 FPGA part number in the Features list. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of...

  • Page 17: Appendix A. Schematics

    LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Appendix A. Schematics Figure 4. LatticeXP2 Standard Evaluation Board...
  • Page 18 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 5. LatticeXP2 Power and Configuration...
  • Page 19 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 6. LatticeXP2 Banks 0 to 3...
  • Page 20 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 7. LatticeXP2 Banks 4 to 7...
  • Page 21 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 8. LatticeXP2 Programming Interfaces...
  • Page 22 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 9. LatticeXP2 Bypass Capacitors...
  • Page 23 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 10. Peripherals and Clock Inputs...
  • Page 24 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 11. D/A, A/D, 7-Segment and RS232...
  • Page 25 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 12. Compact Flash, LVDS, Switches and LCD...
  • Page 26 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 13. Asynchronous SRAM...
  • Page 27 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 14. Prototype Grid...
  • Page 28 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 15. Power Manager...
  • Page 29 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 16. 1.2V Core Supply...
  • Page 30 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 17. 3.3V Power Converter...
  • Page 31 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 18. Adjustable Power Supply...
  • Page 32 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 19. USB Download PHY...
  • Page 33 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 20. MachXO Power...
  • Page 34 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 21. MachXO Banks 0 to 3...
  • Page 35 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 22. MachXO Banks 4 to 7...
  • Page 36 LatticeXP2 Standard Lattice Semiconductor Evaluation Board User’s Guide Figure 23. Placement Proposal rs232...

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