J3
1
2
E4
H2
E5
J2
GND
GND
F5
J1
F6
K1
GND
GND
E3
L1
E2
M1
GND
GND
B1
L3
C1
M3
GND
GND
F2
J4
G2
J5
GND
GND
G4
K5
G5
K4
GND
GND
H4
M5
H50
M4
39
40
© 2011-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02038-1.2
J4
1
2
F3
GND
F4
GND
C3
GND
C2
GND
D2
GND
D1
GND
E1
GND
F1
GND
G3
GND
H3
GND
G1
GND
H1
GND
NC
M2
NC
N2
J3
R1
K3
R2
K2
L5
L2
L4
N1
N4
P1
N3
39
40
Figure 7.2. J3/J4 Header Landing Control
Top Side
J6 J5
Figure 7.3. J5/J6 Header Landing Control
MachXO 2280 Breakout Board Evaluation Kit
Evaluation Board User Guide
J6
1
2
G6
GND
J6
GND
L7
GND
L9
GND
J11
GND
G11
GND
F9
GND
F7
GND
NC
NC
NC
NC
NC
E10
NC
E11
NC
B13
NC
C13
A6
B14
A7
C14
B8
A15
C8
B15
NC
GND
NC
GND
39
40
J5
1
2
B2
D8
B3
E8
A2
E9
A3
A10
D3
C9
D4
C10
C4
D9
C5
D10
D6
B9
D5
B10
B4
A11
B5
A12
E7
B11
E6
B12
A5
C11
A4
C12
C6
A13
C7
A14
B6
D11
B7
D12
39
40
23
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