Pmod Header; Jtag Header; Table 8.6. J17, J18 And J19 Header Pin Connections; Table 8.7. J1 Header Pin Connections - Lattice Semiconductor LIFCL-40-EVN User Manual

CrossLink-NX Evaluation Board
User Guide

8.6. PMOD Header

The J17, J18 and J19 header can be used as GPIO or as a connector to a PMOD interface.

Table 8.6. J17, J18 and J19 Header Pin Connections

Pin Name
J17 Pin Name
1
2
3
4
5
6
7
8
J18 Pin Name
1
2
3
4
5
6
7
8
J19 Pin Name
1
2
3
4
5
6
7
8

8.7. JTAG Header

The J1 header is used to access the JTAG port of the CrossLink-NX or the Raspberry Pi interface.

Table 8.7. J1 Header Pin Connections

J1 Pin Name
1
2
3
4
5
6
7
8
© 2019-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
Signal Name
PMOD0_1
PMOD0_2
PMOD0_3
PMOD0_4
PMOD0_7
PMOD0_8
PMOD0_9
PMOD0_10
PMOD1_1
PMOD1_2
PMOD1_3
PMOD1_4
PMOD1_7
PMOD1_8
PMOD1_9
PMOD1_10
PMOD2_1
PMOD2_2
PMOD2_3
PMOD2_4
PMOD2_7
PMOD2_8
PMOD2_9
PMOD2_10
Signal Name
VCCIO1
TDO
TDI
No Connect
No Connect
TMS
GND
TCK
LIFCL-40 Ball
D10
D9
D7
D8
D6
D5
D4
D3
E10
E9
E7
E8
E4
E3
E2
F1
J2
J1
K2
K1
K3
K4
D17
E18
LIFCL-40 Ball
—
F19
F17
—
—
F15
—
E19
FPGA-EB-02028-1.4