Related Manuals for Lattice Semiconductor LFSC80E-P4-EV
Summary of Contents for Lattice Semiconductor LFSC80E-P4-EV
- Page 1 LatticeSC PCI Express x4 Evaluation Board User’s Guide September 2009 Revision: EB31_01.2...
- Page 2 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Introduction This user’s guide describes the LatticeSC PCI Express x4 Evaluation Board featuring the LatticeSC LFSCM3GA80EP1-6FC1152C FPGA device. This stand-alone evaluation PCB provides a functional platform for development and rapid prototyping of applications that require high-speed SERDES interfaces and/or PCI Express protocols.
-
Page 3: Additional Resources
LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide • On-board and external reference clock sources • Interchangeable clock oscillators • ORCAstra demonstration software interface via standard ispVM JTAG connection • Various high-speed layout structures • User-defined input and output points •... -
Page 4: Applying Power To The Board
LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Note: The connections referenced in this document refer to the LFSCM3GA80 device. Available I/Os and associ- ated sysIO™ banks may differ for other densities within this device family. Applying Power to the Board The LatticeSC PCI Express x4 Evaluation Board is ready to power on. -
Page 5: Programming/Fpga Configuration
LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Programming/FPGA Configuration (see Appendix A, Figure 7) A programming header is provided on the evaluation board, providing access to the LatticeSC JTAG port. ® ® Note: An ispDOWNLOAD Cable is included with each ispLEVER design tool shipment. - Page 6 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide 4. Press the SCAN button located in the toolbar. The LatticeSC device should be automatically detected. Figure 3. ispVM Main Window 5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse...
- Page 7 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 4. Device Information Dialog Box 6. Click the green GO button. This will begin the download process into the device. Upon successful download, the device will be operational. Configuration Status Indicators (see Appendix A, Figure 7) These LEDs indicate the status of configuration to the FPGA.
- Page 8 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide MODE [3:0] (see Appendix A, Figure 7) The FPGA MODE pins are set on the board for a particular programming mode via the SW6 DIP switch. JTAG pro- gramming is independent of the MODE pins and is always available to the user. Pushing in (depressing) the switch is ON and sets the value to 0.
-
Page 9: Serdes Reference Clock
LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide When Y3 or Y5 are enabled, the user should remove Y1 or Y4 respectively to eliminate contention issues between the clock sources. There are several resistor stuffing options that may be needed based on the user’s requirements, R183 and R184 are left OPEN by factory default allowing connection to SMA inputs via R181 and R182. - Page 10 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide B_HDOUTN1_L B_HDOUTP1_L B_HDOUTN2_L B_HDOUTP2_L B_HDOUTN3_L B_HDOUTP3_L PCI Express x1 Cable Connectors PCI Express x1 Cable Connectors (CON1 and CON2) are provided to demonstrate cable capabilities of the SERDES channels. These cable connectors conform with the PCI Express Cable Specifications. A simple cable loopback connected between the connectors can be used to evaluate this feature.
- Page 11 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Logic Analysis Connection (LA1) (see Appendix A, Figure 13) Agilent single-ended probes designed for connection to the supplies. Tyco/AMP’s 2-767004-2 MICTOR connector can be easily attached for signal bus analysis. Connections to general-purpose I/O pins are provided to the board- ready 38-pin MICTOR connector.
- Page 12 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Table 10. Mictor Connector Connections (Continued) Site Signal Mictor Pin # PR80D LA12 PR81A LA13 PR81B LA14 PR81C AA10 LA15 PR81D AB10 LA16 PR82A LA17 PR82B LA18 PR82C LA19 PR82D...
- Page 13 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Table 11. 17-Segment LED Display Segment AC33 AA30 AD34 AA28 AA33 K M N AB34 AA29 Test SMA Connections General-purpose FPGA pins are available via SMA test connections. These connections are designed to permit the evaluation of several FPGA I/O buffer types.
-
Page 14: Ordering Information
01.2 Updated On-Board Flash Memory text section. © 2009 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. -
Page 15: Appendix A. Schematics
LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Appendix A. Schematics Figure 6. Cover Page... - Page 16 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 7. Configuration/Testpoints...
- Page 17 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 8. Power Supplies...
- Page 18 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 9. DC/DC Conversion...
- Page 19 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 10. SERDES...
- Page 20 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 11. DDR2 MemIntf_A[0:12] MemIntf_DQ[0:15] MemIntf_A[0:12]...
- Page 21 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 12. Differential I/O Test SMAs...
- Page 22 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 13. Differential I/O Loops...
- Page 23 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 14. Clocks...
- Page 24 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 15. VSS Decoupling...
- Page 25 LatticeSC PCI Express x4 Evaluation Board Lattice Semiconductor User’s Guide Figure 16. Parallel Flash...