Control Buses - I C, Uart, And Spi; I 2 C; Uart Topology; Figure 6.1. I 2 C Architecture And Uart Options - Lattice Semiconductor LIFCL-40-EVN User Manual

6. Control Buses – I
This section describes the topology of the various configuration and communication buses.
2
6.1. I C
The CrossLink-NX Evaluation Board uses the I
Raspberry Pi communication. The global I
Raspberry Pi header as shown in
Raspberry Pi connector is connected to a dedicated CrossLink-NX GPIO bank with a direct local I
optionally connect to the global I
FTDI 2232H (UI)
2
Table 6.1. I C Global Bus Connections
CrossLink-NX Bank Component
(Reference)
6 Raspberry Pi
header (JP5)

6.2. UART Topology

The board provides support for UART configuration by providing an uninstalled connection between the FTDI and
CrossLink-NX. Two 0 Ω resistors (R16 and R17) can be installed to connect Port 1 to two general purpose I/O (PR8A/F16
and PR10A/F18) in Bank 6 as shown in
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FPGA-EB-02028-1.4
2
C, UART, and SPI
2
C bus to support CrossLink-NX configuration, and optionally to support
2
C bus has the signal names SDA and SCL and they are routed close to
Figure 4.1 and in more detail in
2
C bus through resistors. The local I
SDA
BDBUS1/2
SCL
BDBUS0
2
Instantiated I C
Resistors (R18, R19)
2
Figure 6.1. I C Architecture and UART Options
Header Pin CrossLink-NX -
27
28
Figure 6.1.
Figure 6.1.
2
C connections are summarized in
RASP_ID_SD
Bank6 (U3)
RASP_ID_SC
SDA
SCL
TXD_UART
RXD_UART
Local Signal Name (Global I
85 Ball
M7 RASP_ID_SD (SDA)
M4 RASP_ID_SC (SCL)
CrossLink-NX Evaluation Board
User Guide
2 2
C bus. Local I C bus can
Table .
Bank1 (U3)
2
C Signal) Resistor
R40 (DNI)
R39 (DNI)
19