D-Phy1 Header; Table 8.5. D-Phy1 J6 Header Pin Connections - Lattice Semiconductor LIFCL-40-EVN User Manual

CN1 Pin Name
21
22
23
24
25
26
27
28
29
30

8.5. D-PHY1 Header

Table 8.5. D-PHY1 J6 Header Pin Connections

J6 Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
© 2019-2021 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02028-1.4
Signal Name
NO Connect
CAM_SDA
CAM_SCL
CAM_RESET
V1P2
V1P8
GND
GND
V2P8
GND
Signal Name
GND
GND
DPHY1_CKP
DPHY1_CKN
GND
GND
DPHY1_DP0
DPHY1_DN0
GND
GND
DPHY1_DP1
DPHY1_DN1
GND
GND
DPHY1_DP2
DPHY1_DN2
GND
GND
DPHY1_DP3
DPHY1_DN3
CrossLink-NX Evaluation Board
User Guide
LIFCL-40 Ball
—
W5
Y5
W18
—
—
—
—
—
—
LIFCL-40 Ball
—
—
A8
B8
—
—
A7
B7
—
—
A9
B9
—
—
A6
B6
—
—
A10
B10
27