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The LatticeECP3 Versa Evaluation Board is part of the LatticeECP3 Versa Development Kit. The guide is intended to be referenced in conjunction with demo user’s guides to demonstrate the LatticeECP3 FPGA.
Note: The connections referenced in this document refer to the LFE3-35EA-8FN484C device. Applying Power to the Board The LatticeECP3 Versa Evaluation Board is ready to power on. The board can be supplied with power from a PCI Express host system or standalone with an external wall power module.
LatticeECP3 Versa Evaluation Board User’s Guide Alternate ispVM Download Interface J3 is a 1x10 100mil header that is provided for use with an external Lattice download cable (available separately). A USB download cable can be attached to the board using J3 to interface with the FPGA (U1).
PROGRAMN with a bitstream stored in the memory device. 1. Connect the LatticeECP3 Versa Evaluation Board. 2. In the dialog box, select SPI Flash Programming Mode in the Device Access Option pull-down menu.
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LatticeECP3 Versa Evaluation Board User’s Guide Figure 4. Device Information Dialog Screen 3. The SPI Serial Flash Device dialog box will open. In this box, select SPI Flash Erase, Program, Verify in the Operation pull-down menu. 4. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu, SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu.
On-Board Clock Capabilities (See Appendix B, Figure 19) The LatticeECP3 Versa Evaluation Board allows for several clock source options. Some of these options are con- trolled via the ispClock5406A programmable clock manager device. The ispClock5406A enables the reference clock from the PCI Express interface to provide a reference clock to the SERDES. This is true only when the board is in a PCI Express host socket.
The PCI Express add-in card specification requires add-in boards to include capabilities to tell the host of its pres- ence. The LatticeECP3 Versa Evaluation Board allows this optional connection via a board jumper. The factory default will have two jumpers installed as shown below for the PRSNT connection to the PCI Express host.
(See Appendix B, Figure 18) The LEDs provided on the LatticeECP3 Versa Evaluation Board are connected to general purpose FPGA I/Os. These LEDs provide status for user designs and must be included in the design. The LEDs illuminate when the FPGA output is driven LOW.
DDR3 Memory Device (see Appendix B, Figure 17) • The LatticeECP3 Versa Evaluation Board is equipped with a SDRAM memory device (1.5V, 64Mb/x16, 96-ball FBGA, 667 MHz, DDR3-1333) such as the Micron MT41J64M16JT-15E:G device. • The DDR3 memory includes a 16-bit wide memory controller interface.
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