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Table 7.1
describes the components on the board and the interfaces it supports.
Table 7.1. Breakout Board Components and Interfaces
Component/Interface
Type
Circuits
USB Controller
Circuit
USB Mini-B Socket
I/O
Components
LCMXO2
FPGA
Interfaces
LED Array
Output
Four 2 × 20 Header
I/O
Landings
1 × 8 Header Landing
I/O
4 × 15 60-Hole
—
Prototype Area
Test Points
Power
7.2. Subsystems
This section describes the principle subsystems for the Breakout Board in alphabetical order.
7.2.1. Clock Sources
All clocks for the counter demonstration designs originate from the MachXO2 on-chip oscillator. You may use an
expansion header landing to drive a FPGA input with an external clock source.
7.2.2. Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the MachXO2.
The remaining pins serve as power supplies for external connections. Each landing is configured as one 2 x 20 100 mil.
Table 7.2. Expansion Connector Reference
Reference Designators
© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3
Schematic Reference
U2: FT2232H
J7:USB_MINI_B
U3: LCMXO2-7000HE-
4TG144C
D8-D1
J2: header_2x20
J3: header_2x20
J4: header_2x20
J5: header_2x20
J1: header_1x8
—
TP1: +3.3 V
TP2: +1.2 V
TP3: GND
Item
Part Number
MachXO2 Breakout Board Evaluation Kit
Description
USB-to-JTAG interface and dual USB UART/FIFO IC
Programming and debug interface
7000-LUT device packaged in a 20 x 20mm, 144-pin TQFP
Red LEDs
User-definable I/O
Optional JTAG interface
Prototype area 100mil centered holes.
Power and ground reference points
header_2x20
Evaluation Board User Guide
Description
J2, J3, J4, J5
13
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