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Figure 3.3. Level Shift For Jtag Download Interface; Figure 3.4. Jtag Test Header; Table 3.1. Config Jtag Connections - Lattice Semiconductor MachXO5-NX User Manual

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output tri-state mode, avoiding multi-drivers on those shared signals. The JTAG connections between J1 and

MachXO5-25 are listed in

Table

Table 3.1. Config JTAG Connections

J1 Pin Number

1

2

3

4

5

6

7

8

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-EB-02052-0.90

3.1.

Figure 3.3. Level Shift for JTAG Download Interface

Figure 3.4. JTAG Test Header

JTAG Net Name

VCCIO2

NX_TDO

NX_TDI

—

—

NX_TMS

GND

NX_TCK

MachXO5-NX Development Board

Preliminary Evaluation Board User Guide

MachXO5-25 Ball Location

for JTAG

—

E20

E18

—

—

F16

—

G16

Optional SSPI Function

—

SSI

SSO

—

—

SCSN

—

SCLK

13

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